Restructured UART directory

2025-09-07 01:59:51 -07:00
parent 465055fc53
commit 06f0b9303c
5 changed files with 2 additions and 2 deletions
--- a/SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_F072xB.h
+++ b/SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_F072xB.h
@@ -0,0 +1,105 @@
+//
+// Created by Luca on 9/7/2025.
+//
+
+#ifndef SHMINGO_HAL_SHAL_UART_REG_F072XB_H
+#define SHMINGO_HAL_SHAL_UART_REG_F072XB_H
+
+#include <stm32f072xb.h>
+#include <cassert>
+
+#include "SHAL_UART_TYPES.h"
+#include "SHAL_GPIO_REG.h"
+
+#define NUM_USART_LINES 4
+
+//Valid usart Tx and Rx pairings for STM32F072
+enum class UART_Pair : uint8_t{
+    //UART1
+    Tx1A9_Rx1A10,
+    Tx1B6_Rx1B7,
+
+    //UART2
+    Tx2A2_Rx2A3,
+    Tx2A14_Rx2A15,
+
+    //UART3
+    Tx3B10_Rx3B11,
+    Tx3C4_Rx3C5,
+    Tx3C10_Rx3C11,
+
+    //UART4
+    Tx4A0_Rx4A1,
+    Tx4C10_Rx4C11,
+
+    NUM_PAIRS,
+    INVALID
+};
+
+
+constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){
+    switch(pair){
+        case UART_Pair::Tx1A9_Rx1A10: return {USART1,GPIO_Key::A9,GPIO_Key::A10,AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx1B6_Rx1B7: return {USART1,GPIO_Key::B6,GPIO_Key::B7,AF_Mask::AF0,AF_Mask::AF0};
+        case UART_Pair::Tx2A2_Rx2A3: return {USART2,GPIO_Key::A2,GPIO_Key::A3,AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx2A14_Rx2A15: return {USART2,GPIO_Key::A14,GPIO_Key::A15,AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx3B10_Rx3B11: return {USART3,GPIO_Key::B10,GPIO_Key::B11,AF_Mask::AF4,AF_Mask::AF4};
+        case UART_Pair::Tx3C4_Rx3C5: return {USART3,GPIO_Key::C4,GPIO_Key::C5,AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx3C10_Rx3C11: return {USART3,GPIO_Key::C10,GPIO_Key::C11,AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx4A0_Rx4A1: return {USART4,GPIO_Key::A0,GPIO_Key::A1,AF_Mask::AF4,AF_Mask::AF4};
+        case UART_Pair::Tx4C10_Rx4C11: return {USART4,GPIO_Key::C10,GPIO_Key::C11,AF_Mask::AF0,AF_Mask::AF0};
+        case UART_Pair::NUM_PAIRS:
+        case UART_Pair::INVALID:
+            assert(false);
+            return {nullptr,GPIO_Key::INVALID,GPIO_Key::INVALID,AF_Mask::AF0,AF_Mask::AF0};
+    }
+    __builtin_unreachable();
+}
+
+constexpr uint8_t getUARTChannel(const UART_Pair pair){
+    switch(pair){
+        case UART_Pair::Tx1A9_Rx1A10:
+        case UART_Pair::Tx1B6_Rx1B7:
+            return 0;
+        case UART_Pair::Tx2A2_Rx2A3:
+        case UART_Pair::Tx2A14_Rx2A15:
+            return 1;
+        case UART_Pair::Tx3B10_Rx3B11:
+        case UART_Pair::Tx3C4_Rx3C5:
+        case UART_Pair::Tx3C10_Rx3C11:
+            return 2;
+        case UART_Pair::Tx4A0_Rx4A1:
+        case UART_Pair::Tx4C10_Rx4C11:
+            return 3;
+        case UART_Pair::NUM_PAIRS:
+        case UART_Pair::INVALID:
+            assert(false);
+            return 0;
+    }
+    __builtin_unreachable();
+}
+
+constexpr SHAL_UART_ENABLE_REG getUARTEnableReg(const UART_Pair pair){
+    switch(pair){
+        case UART_Pair::Tx1A9_Rx1A10:
+        case UART_Pair::Tx1B6_Rx1B7:
+            return {&RCC->APB2ENR,RCC_APB2ENR_USART1EN};
+        case UART_Pair::Tx2A2_Rx2A3:
+        case UART_Pair::Tx2A14_Rx2A15:
+            return {&RCC->APB1ENR,RCC_APB1ENR_USART2EN};
+        case UART_Pair::Tx3B10_Rx3B11:
+        case UART_Pair::Tx3C4_Rx3C5:
+        case UART_Pair::Tx3C10_Rx3C11:
+            return {&RCC->APB1ENR,RCC_APB1ENR_USART3EN};
+        case UART_Pair::Tx4A0_Rx4A1:
+        case UART_Pair::Tx4C10_Rx4C11:
+            return {&RCC->APB1ENR,RCC_APB1ENR_USART4EN};
+        case UART_Pair::NUM_PAIRS:
+        case UART_Pair::INVALID:
+            assert(false);
+            return {nullptr, 0};
+    }
+    __builtin_unreachable();
+}
+
+#endif //SHMINGO_HAL_SHAL_UART_REG_F072XB_H