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Test program done

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This commit is contained in:
Luca Lizaranzu
2026-03-20 11:41:44 -07:00
parent 303a554595
commit 1b29371fff
20 changed files with 1037 additions and 114 deletions
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213
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_H753ZI.h Normal file
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@@ -0,0 +1,213 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H
#define SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H
#include "SHAL_CORE.h"
#include "SHAL_ADC_TYPES.h"
#include "stm32h753xx.h"
#define SHAL_ADC1 SHAL_ADC(1)
#define SHAL_ADC2 SHAL_ADC(2)
#define SHAL_ADC3 SHAL_ADC(3)
#define NUM_ADCS 3
#define NUM_ADC_CHANNELS 16
enum class SHAL_ADC_Channel : uint32_t {
CH0 = 0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
CH8,
CH9,
CH10,
CH11,
CH12,
CH13,
CH14,
CH15,
CH16,
CH17,
CH18,
CHTemp,
CHRef,
CHBat,
NO_ADC_MAPPING
};
enum class ADC_Key : uint8_t{
S_ADC1 = 0,
S_ADC2 = 1,
S_ADC3 = 2,
NUM_ADC = 3,
INVALID = 255
};
enum class SHAL_ADC_Resolution : uint8_t { //TODO figure out what to do with this difference
B16 = 0x00,
B14 = 0x01,
B12 = 0x02,
B10 = 0x03,
B8 = 0x04,
B6 = 0x05,
};
enum class SHAL_ADC_Clock_Mode {
ASYNC = 0x00,
SYNC_BY_1 = 0x01,
SYNC_BY_2 = 0x02,
SYNC_BY_4 = 0x03,
};
static volatile ADC_TypeDef* ADC_TABLE[3] = { //Lookup table for ADCs
ADC1,
ADC2,
ADC3,
};
static volatile ADC_Common_TypeDef* ADC_CCR_TABLE[3] = { //Common registers
ADC12_COMMON, //1 and 2 share a common register
ADC12_COMMON,
ADC3_COMMON,
};
enum class ADC_Clock_Source : uint32_t {
SHAL_NO_CLOCK = 0x00,
SHAL_PLLSAI1 = 0x01,
SHAL_PLLSYS = 0x02,
SHAL_SYSCLK = 0x03,
};
static SHAL_ADC_Common_Control_Reg getADCCommonControl(ADC_Key key) {
SHAL_ADC_Common_Control_Reg res = {
.reg = nullptr,
.VoltageRefEnable = ADC_CCR_VREFEN,
.TempSensorEnable = ADC_CCR_TSEN,
.VBatteryEnable = ADC_CCR_VBATEN,
.clock_mode_position = ADC_CCR_CKMODE_Pos
};
res.reg = &ADC_CCR_TABLE[static_cast<uint8_t>(key)]->CCR;
return res;
}
static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(const ADC_Key key){
switch (key) {
case ADC_Key::S_ADC1:
case ADC_Key::S_ADC2:
return {&RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN};
case ADC_Key::S_ADC3:
return {&RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN};
default:
__builtin_unreachable();
}
}
static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN,
ADC_CR_ADSTP,
ADC_CR_ADDIS,
ADC_CR_ADCAL,
ADC_CR_ADSTART,
ADC_CR_DEEPPWD,
ADC_CR_ADVREGEN,
ADC_CR_ADCALDIF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
return res;
}
static inline SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
//NOTE offset of 33 means the function is deprecated
SHAL_ADC_Config_Reg res = {nullptr,
ADC_CFGR_CONT,
ADC_CFGR_RES_Pos,
0, //TODO 0 is broken, shouldnt have alignment
ADC_CFGR_CONT_Msk
};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CFGR);
return res;
}
static inline SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
SHAL_ADC_ISR_Reg res = {nullptr,
ADC_ISR_EOC,
ADC_ISR_EOS,
ADC_ISR_ADRDY,
ADC_ISR_OVR,
ADC_ISR_LDORDY};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
return res;
}
static inline SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* SMPReg = nullptr;
uint32_t pos;
auto channelNum = static_cast<uint8_t>(channel);
if (channelNum <= 9) {
SMPReg = &ADCReg->SMPR1;
pos = (channelNum * 3);
} else {
SMPReg = &ADCReg->SMPR2;
pos = ((channelNum - 10) * 3);
}
return {SMPReg, pos};
}
static inline SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
return res;
}
static SHAL_ADC_Sequence_Reg getADCSequenceRegister(ADC_Key key, uint32_t conversionNum){
volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* sqr[4] = {&adc_reg->SQR1,
&adc_reg->SQR2,
&adc_reg->SQR3,
&adc_reg->SQR4,
};
const uint8_t sqrIndex = conversionNum / 5; //CONVERSION NUM STARTS AT 1! AS PER DATASHEET REFERENCING IT AS SQ1
const uint32_t offset = (((conversionNum) % 5) * 6);
return {sqr[sqrIndex], offset};
}
static SHAL_ADC_Preselect_Reg getADCPreselectRegister(ADC_Key key, SHAL_ADC_Channel channel) {
SHAL_ADC_Preselect_Reg res = {nullptr, static_cast<uint32_t>(channel)};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->PCSEL);
return res;
}
#endif //SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H

29
SHAL/Include/Peripheral/ADC/SHAL_ADC.h
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@@ -16,19 +16,21 @@ class SHAL_ADC {
public:
SHAL_Result init(ADC_Key key);
SHAL_Result init(ADC_Key key, SHAL_ADC_Sample_Mode mode);
SHAL_Result calibrate();
SHAL_Result calibrate(SHAL_ADC_Sample_Mode sampleMode) const;
SHAL_Result configureResolution(SHAL_ADC_Resolution resolution);
SHAL_Result configureResolution(SHAL_ADC_Resolution resolution) const;
SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment);
SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment) const;
SHAL_Result preselectChannel(SHAL_ADC_Channel channel) const;
/// Performs analog to digital conversion on a single channel, one time
/// \param channel Channel to be converted
/// \param time SHAL_ADC_SampleTime - amount of clock cycles per conversion
/// \return resulting value
uint16_t singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8);
uint32_t singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8) const;
/// Performs analog to digital conversion on multiple channels, one time
/// \param channels Pointer to an array of channels to convert
@@ -46,29 +48,29 @@ private:
ADC_Key m_ADCKey = ADC_Key::INVALID;
//Checks to see if instance is initialized with a proper ADC peripheral tag
bool isValid();
bool isValid() const;
//Enabled peripheral
SHAL_Result enable();
SHAL_Result enable() const;
//Disables peripheral
SHAL_Result disable();
SHAL_Result disable() const;
//Wake up ADC from initial deep sleep state
SHAL_Result wakeFromDeepSleep();
SHAL_Result wakeFromDeepSleep() const;
SHAL_Result startConversion();
SHAL_Result startConversion() const;
/// Adds an ADC channel to the conversion sequence
/// \param channel Channel to add
/// \param index Index to add channel to (ADC channel will be the nth channel to convert
/// \param conversionNumber Index to add channel to (ADC channel will be the nth channel to convert
/// \return Result
SHAL_Result addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t index);
SHAL_Result addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t conversionNumber) const;
/// Sets the amount of ADC channels to convert
/// \param amount Number of channels to convert
/// \return
SHAL_Result setADCSequenceAmount(uint32_t amount);
SHAL_Result setADCSequenceAmount(uint32_t amount) const;
};
@@ -83,7 +85,6 @@ public:
static SHAL_ADC& getByIndex(int index);
ADCManager() = delete;
private:

44
SHAL/Include/Peripheral/ADC/SHAL_ADC_REG.h
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@@ -88,6 +88,50 @@
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#elif defined(STM32H743xx)
#include "stm32h743xx.h"
#elif defined(STM32H753xx)
#include "SHAL_ADC_REG_H753ZI.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H745xG)
#include "stm32h745xg.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H747xG)
#include "stm32h747xg.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

26
SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
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@@ -5,12 +5,15 @@
#ifndef SHMINGO_HAL_SHAL_ADC_TYPES_H
#define SHMINGO_HAL_SHAL_ADC_TYPES_H
#include "SHAL_CORE.h"
//Common register among all ADC peripherals
struct SHAL_ADC_Common_Control_Reg {
volatile uint32_t* reg;
uint32_t VoltageRefEnable;
uint32_t TempSensorEnable;
uint32_t VBatteryEnable;
uint32_t clock_mode_position;
};
//Register controlling the ADC peripheral clock
@@ -29,7 +32,7 @@ struct SHAL_ADC_Control_Reg {
uint32_t start_mask;
uint32_t deep_power_down_mask;
uint32_t voltage_regulator_mask;
uint32_t differential_mode_mask;
uint32_t sample_mode_offset;
};
//Register controlling ADC configuration
@@ -55,6 +58,7 @@ struct SHAL_ADC_ISR_Reg {
uint32_t end_of_sequence_mask;
uint32_t ready_mask;
uint32_t overrun_mask;
uint32_t ldo_ready_mask;
};
//Register controlling the clock source for the ADC
@@ -79,9 +83,13 @@ struct SHAL_ADC_Sequence_Amount_Reg {
*reg 1 + offset 1
*Any sections after the last one (for example, max for a 16 channel register is reg 4 offset 2*/
struct SHAL_ADC_Sequence_Reg {
volatile uint32_t* regs[6];
volatile uint32_t* reg;
uint32_t sequence_offset;
};
uint32_t offsets[5];
struct SHAL_ADC_Preselect_Reg {
volatile uint32_t* reg;
uint32_t channel_offset;
};
@@ -98,16 +106,14 @@ enum class SHAL_ADC_SampleTime : uint32_t {
C8 = 0x07 //239.5 cycles
};
enum class SHAL_ADC_Resolution : uint8_t {
B12 = 0x00,
B10 = 0x01,
B8 = 0x02,
B6 = 0x03,
};
enum class SHAL_ADC_Alignment : uint8_t {
RIGHT = 0x00,
LEFT = 0x01,
};
enum class SHAL_ADC_Sample_Mode {
SINGLE_ENDED = 0,
DIFFERENTIAL = 1,
};
#endif //SHMINGO_HAL_SHAL_ADC_TYPES_H