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Refactors for L432KC done for all peripherals except GPIO

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This commit is contained in:
Ea-r-th
2025-10-19 01:49:13 -07:00
parent e822b8d9ec
commit 2c5592c2d3
16 changed files with 207 additions and 76 deletions
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36
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_L432KC.h
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@@ -43,11 +43,11 @@ enum class ADC_Key : uint8_t{
INVALID = 255
};
enum class ADC_Clock_Source : uint8_t {
SHAL_SYSCLK,
SHAL_PLLSAI1,
SHAL_PLL,
SHAL_MSI
enum class ADC_Clock_Source : uint32_t {
SHAL_NO_CLOCK = 0x00,
SHAL_PLLSAI1 = 0x01,
SHAL_PLLSYS = 0x02,
SHAL_SYSCLK = 0x03,
};
static volatile ADC_TypeDef* ADC_TABLE[1] = { //Lookup table for ADCs
@@ -59,15 +59,21 @@ static inline SHAL_ADC_Common_Control_Reg getADCCommonControl() {
}
static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
SHAL_ADC_RCC_Enable_Reg res = {nullptr, RCC_AHB2ENR_ADCEN};
SHAL_ADC_RCC_Enable_Reg res = {&RCC->AHB2ENR, RCC_AHB2ENR_ADCEN};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN, ADC_CR_ADDIS, ADC_CR_ADCAL, ADC_CR_ADSTART};
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN,
ADC_CR_ADSTP,
ADC_CR_ADDIS,
ADC_CR_ADCAL,
ADC_CR_ADSTART,
ADC_CR_DEEPPWD,
ADC_CR_ADVREGEN,
ADC_CR_ADCALDIF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
return res;
@@ -95,19 +101,9 @@ static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
return res;
}
static inline SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Msk, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
static inline SHAL_ADC_Clock_Reg getADCClockSelectRegister() {
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Pos}; //Position
switch(clockSource){
case ADC_Clock_Source::SHAL_PLLSAI1:
res.mask = 1U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_PLL:
res.mask = 2U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_SYSCLK:
res.mask = 3U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_MSI:
break; //TODO implement this
}
return res;
}

5
SHAL/Include/Peripheral/ADC/SHAL_ADC.h
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@@ -16,7 +16,7 @@ class SHAL_ADC {
public:
SHAL_Result init();
SHAL_Result init(ADC_Key key);
SHAL_Result calibrate();
@@ -54,6 +54,9 @@ private:
//Disables peripheral
SHAL_Result disable();
//Wake up ADC from initial deep sleep state
SHAL_Result wakeFromDeepSleep();
SHAL_Result startConversion();
/// Adds an ADC channel to the conversion sequence

7
SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
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@@ -23,9 +23,13 @@ struct SHAL_ADC_RCC_Enable_Reg {
struct SHAL_ADC_Control_Reg {
volatile uint32_t* reg;
uint32_t enable_mask;
uint32_t stop_mask;
uint32_t disable_mask;
uint32_t calibration_mask;
uint32_t start_mask;
uint32_t deep_power_down_mask;
uint32_t voltage_regulator_mask;
uint32_t differential_mode_mask;
};
//Register controlling ADC configuration
@@ -54,8 +58,7 @@ struct SHAL_ADC_ISR_Reg {
//Register controlling the clock source for the ADC
struct SHAL_ADC_Clock_Reg {
volatile uint32_t* reg;
uint32_t clear;
uint32_t mask;
uint32_t offset;
};
//Register controlling the sampling time of ADC samples

2
SHAL/Include/Peripheral/EXT/Reg/SHAL_EXTI_REG_L432KC.h
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@@ -11,7 +11,7 @@
#define EXTI_PENDING_REG(line) ((line) < 32 ? EXTI->PR1 : EXTI->PR2)
static inline SHAL_EXTI_Interrupt_Mask_Register getEXTIInterruptMaskRegister(uint32_t line){
auto imr = line < 32 ? EXTI->IMR1 : EXTI->IMR2;
uint32_t imr = line < 32 ? EXTI->IMR1 : EXTI->IMR2;
return {&imr};
}

3
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_L432KC.h
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@@ -10,7 +10,7 @@
#include "SHAL_GPIO_TYPES.h"
#define AVAILABLE_PORTS 3
#define AVAILABLE_PORTS 2
#define PINS_PER_PORT 16
#define NUM_EXTI_LINES 16
@@ -157,6 +157,7 @@ constexpr uint32_t getGPIOPortNumber(const GPIO_Key g){
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
return 1;
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);

4
SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_L432KC.h
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@@ -81,14 +81,14 @@ static inline SHAL_UART_Control_Register_1 getUARTControlRegister1(UART_Pair_Key
};
static inline SHAL_UART_Baud_Rate_Generation_Register getUARTBaudRateGenerationRegister(UART_Pair_Key key){
SHAL_UART_Baud_Rate_Generation_Register res = {nullptr, 1UL << 15}; //TODO un-hardcode if other devices have wider baud rate allowances
SHAL_UART_Baud_Rate_Generation_Register res = {nullptr}; //TODO un-hardcode if other devices have wider baud rate allowances
res.reg = &getUARTPair(key).USARTReg->BRR;
return res;
};
static inline SHAL_UART_Transmit_Data_Register getUARTTransmitDataRegister(UART_Pair_Key key){
SHAL_UART_Transmit_Data_Register res = {nullptr, 1UL << 15}; //TODO un-hardcode if other devices have wider baud rate allowances
SHAL_UART_Transmit_Data_Register res = {nullptr}; //TODO un-hardcode if other devices have wider baud rate allowances
res.reg = &getUARTPair(key).USARTReg->TDR;
return res;

2
SHAL/Include/Peripheral/UART/SHAL_UART_TYPES.h
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@@ -33,12 +33,10 @@ struct SHAL_UART_Control_Register_1 {
struct SHAL_UART_Baud_Rate_Generation_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_UART_Transmit_Data_Register {
volatile uint16_t* reg;
uint16_t offset;
};
struct SHAL_UART_ISR_FIFO_Disabled {