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Refactors for L432KC done for all peripherals except GPIO

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This commit is contained in:
Ea-r-th
2025-10-19 01:49:13 -07:00
parent e822b8d9ec
commit 2c5592c2d3
16 changed files with 207 additions and 76 deletions
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129
SHAL/Src/STM32L4XX/Peripheral/ADC/SHAL_ADC.cpp
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@@ -3,30 +3,41 @@
//
#include "SHAL_ADC.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART.h"
#include <cstdio>
//Can hard code registers on F0 because all F0 devices have only one ADC, and use only one clock
SHAL_Result SHAL_ADC::init() {
SHAL_Result SHAL_ADC::init(ADC_Key key) {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
m_ADCKey = key;
if(!isValid()){
SHAL_UART2.sendString("Not valid\r\n");
return SHAL_Result::ERROR;
}
SHAL_UART2.sendString("Init called\r\n");
PIN(B4).toggle();
SHAL_delay_ms(100);
PIN(B4).toggle();
SHAL_ADC_RCC_Enable_Reg clock_reg = getADCRCCEnableRegister(m_ADCKey); //Clock enable
*clock_reg.reg |= clock_reg.mask;
SHAL_apply_bitmask(clock_reg.reg,clock_reg.mask);
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
auto clock_select_register = getADCClockSelectRegister();
if (*control_reg.reg & control_reg.enable_mask) {
//request disable: ADEN=1 -> set ADDIS to disable
*control_reg.reg |= control_reg.disable_mask;
//wait until ADEN cleared (ISR.ADREADY == 0)
if(!SHAL_WAIT_FOR_CONDITION_MS((*control_reg.reg & control_reg.enable_mask) == 0, 100)){
return SHAL_Result::ERROR;
}
}
SHAL_set_bits(clock_select_register.reg, 2, static_cast<uint32_t>(ADC_Clock_Source::SHAL_SYSCLK),clock_select_register.offset); //Set ADC clock
wakeFromDeepSleep();
if(calibrate() != SHAL_Result::OKAY){ //Calibrate
SHAL_UART2.sendString("Calibration failed");
return SHAL_Result::ERROR;
}
if(enable() != SHAL_Result::OKAY){
SHAL_UART2.sendString("Could not enable from init\r\n");
return SHAL_Result::ERROR;
}
@@ -37,19 +48,31 @@ SHAL_Result SHAL_ADC::init() {
}
SHAL_Result SHAL_ADC::calibrate() {
if(disable() != SHAL_Result::OKAY){ //Disable the ADC
return SHAL_Result::ERROR;
}
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
*control_reg.reg |= control_reg.calibration_mask;
if(!SHAL_WAIT_FOR_CONDITION_US(((*control_reg.reg & control_reg.calibration_mask) == 0),500)){ //Wait for calibration
if(disable() != SHAL_Result::OKAY){
return SHAL_Result::ERROR;
}
SHAL_delay_us(1000);
if ((*control_reg.reg & (control_reg.enable_mask | control_reg.disable_mask)) != 0) {
return SHAL_Result::ERROR;
}
SHAL_clear_bitmask(control_reg.reg, control_reg.differential_mode_mask);
SHAL_apply_bitmask(control_reg.reg, control_reg.calibration_mask);
if ((*control_reg.reg & control_reg.calibration_mask) == 0) {
return SHAL_Result::ERROR;
}
if (!SHAL_WAIT_FOR_CONDITION_US(((*control_reg.reg & control_reg.calibration_mask) != 0),500)) { //Wait for conversion
return SHAL_Result::ERROR; //Failed sequence
}
SHAL_UART2.sendString("Calibration OK\r\n");
return SHAL_Result::OKAY;
}
@@ -118,33 +141,70 @@ SHAL_Result SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, const int n
SHAL_Result SHAL_ADC::enable() {
if(!isValid()){
SHAL_UART2.sendString("Enable failed: Invalid \r\n");
return SHAL_Result::ERROR;
}
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
*control_reg.reg |= control_reg.enable_mask; //Enable
if(!SHAL_WAIT_FOR_CONDITION_MS((*ISR_reg.reg & ISR_reg.ready_mask) != 0, 100)){
if(!SHAL_WAIT_FOR_CONDITION_MS((*control_reg.reg & control_reg.calibration_mask) == 0, 100)) {
return SHAL_Result::ERROR;
}
if (*control_reg.reg & control_reg.enable_mask) {
return SHAL_Result::OKAY; //Not an error
}
if (*control_reg.reg & control_reg.disable_mask) {
return SHAL_Result::ERROR;
}
//Clear ADRDY flag by writing 1 to it
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask);
//Enable the ADC by setting ADEN
SHAL_apply_bitmask(control_reg.reg, control_reg.enable_mask);
if(!SHAL_WAIT_FOR_CONDITION_MS((*ISR_reg.reg & ISR_reg.ready_mask) != 0, 100)) {
return SHAL_Result::ERROR;
}
//Clear ADRDY again
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::wakeFromDeepSleep() {
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey); //ADC Control register
SHAL_clear_bitmask(control_reg.reg,control_reg.deep_power_down_mask); //Wake ADC from sleep
SHAL_apply_bitmask(control_reg.reg,control_reg.voltage_regulator_mask);
SHAL_delay_us(50); //Wait for regulator to stabilize
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::disable() {
if(!isValid()){
return SHAL_Result::ERROR;
}
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
auto control_reg = getADCControlReg(m_ADCKey);
//Stop any ongoing conversion
if (*control_reg.reg & control_reg.start_mask) {
SHAL_apply_bitmask(control_reg.reg, control_reg.stop_mask);
}
//Only disable if ADC is enabled otherwise it hangs
if (*control_reg.reg & control_reg.enable_mask) {
//request disable: ADEN=1 -> set ADDIS to disable
*control_reg.reg |= control_reg.disable_mask;
//wait until ADEN cleared (ISR.ADREADY == 0)
if(!SHAL_WAIT_FOR_CONDITION_MS((*control_reg.reg & control_reg.enable_mask) == 0, 100)){
SHAL_apply_bitmask(control_reg.reg, control_reg.disable_mask);
if (!SHAL_WAIT_FOR_CONDITION_MS(((*control_reg.reg & (control_reg.enable_mask | control_reg.disable_mask)) == 0),500)){
return SHAL_Result::ERROR;
}
}
@@ -152,6 +212,7 @@ SHAL_Result SHAL_ADC::disable() {
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::startConversion() {
auto control_reg = getADCControlReg(m_ADCKey);
@@ -186,8 +247,8 @@ SHAL_Result SHAL_ADC::configureAlignment(SHAL_ADC_Alignment alignment) {
SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
*config_reg.reg &= ~(0x1UL << config_reg.alignment_offset); //TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
*config_reg.reg |= static_cast<uint8_t>(alignment) << config_reg.alignment_offset;
//TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
SHAL_set_bits(config_reg.reg,1,static_cast<uint8_t>(alignment),config_reg.alignment_offset);
return SHAL_Result::OKAY;
}
@@ -220,9 +281,13 @@ SHAL_Result SHAL_ADC::addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t
uint32_t bitSectionOffset = sequenceRegisters.offsets[bitSection];
SHAL_set_bits(sequenceReg,5,channelNum,bitSectionOffset);
return SHAL_Result::OKAY;
}
SHAL_ADC &ADCManager::get(ADC_Key key) {
return m_ADCs[static_cast<uint8_t>(key)];
}