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Changed bitmask to offset in peripheral struct to support different register patterns

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This commit is contained in:
Luca Lizaranzu
2025-08-30 15:54:42 -07:00
parent 19fbe6c0ad
commit 2da3413329
7 changed files with 107 additions and 24 deletions
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2
SHAL/Include/Core/SHAL_CORE.h
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@@ -15,7 +15,7 @@
struct SHAL_Peripheral {
volatile uint32_t* reg;
uint32_t bitmask;
unsigned long offset;
};

86
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h Normal file
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@@ -0,0 +1,86 @@
//
// Created by Luca on 8/29/2025.
//
#ifndef SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H
#define SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H
#include <stm32f072xb.h>
#include <cassert>
#define AVAILABLE_GPIO \
X(A0) X(A1) X(A2) X(A3) X(A4) X(A5) X(A6) X(A7) X(A8) X(A9) X(A10) X(A11) X(A12) X(A13) X(A14) X(A15) \
X(B0) X(B1) X(B2) X(B3) X(B4) X(B5) X(B6) X(B7) X(B8) X(B9) X(B10) X(B11) X(B12) X(B13) X(B14) X(B15) \
X(C0) X(C1) X(C2) X(C3) X(C4) X(C5) X(C6) X(C7) X(C8) X(C9) X(C10) X(C11) X(C12) X(C13) X(C14) X(C15)
//Build enum map of available GPIO pins
enum class GPIO_Key {
#define X(key) key,
AVAILABLE_GPIO
#undef X
NUM_GPIO,
INVALID
};
constexpr volatile GPIO_TypeDef* getGPIORegister(GPIO_Key g) {
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return GPIOA;
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return GPIOB;
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return GPIOC;
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return nullptr; //Unreachable
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H

3
SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
View File

@@ -5,6 +5,9 @@
#ifndef SHMINGO_HAL_SHAL_GPIO_H
#define SHMINGO_HAL_SHAL_GPIO_H
#include "SHAL_CORE.h"
#include <cassert>
#include <stm32f072xb.h>
#endif //SHMINGO_HAL_SHAL_GPIO_H

14
SHAL/Include/Peripheral/GPIO/SHAL_GPIO_REG.h
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@@ -1,14 +0,0 @@
//
// Created by Luca on 8/29/2025.
//
#ifndef SHMINGO_HAL_SHAL_GPIO_REG_H
#define SHMINGO_HAL_SHAL_GPIO_REG_H
enum class GPIO_Key {
A0,
A1,
};
#endif //SHMINGO_HAL_SHAL_GPIO_REG_H

22
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_F072xB.h
View File

@@ -18,6 +18,8 @@ enum class Timer_Key { //For STM32F072
S_TIM1,
S_TIM2,
S_TIM3,
S_TIM6,
S_TIM7,
S_TIM14,
S_TIM15,
S_TIM16,
@@ -30,13 +32,15 @@ enum class Timer_Key { //For STM32F072
//Get timer peripheral struct including bus register, enable mask, timer mask
constexpr SHAL_Peripheral getTimerRCC(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR, RCC_APB1ENR_TIM2EN};
case Timer_Key::S_TIM3: return {&RCC->APB1ENR, RCC_APB1ENR_TIM3EN};
case Timer_Key::S_TIM14: return {&RCC->APB1ENR, RCC_APB1ENR_TIM14EN};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_Pos};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR, RCC_APB1ENR_TIM2EN_Pos};
case Timer_Key::S_TIM3: return {&RCC->APB1ENR, RCC_APB1ENR_TIM3EN_Pos};
case Timer_Key::S_TIM6: return {&RCC->APB1ENR, RCC_APB1ENR_TIM6EN_Pos};
case Timer_Key::S_TIM7: return {&RCC->APB1ENR, RCC_APB1ENR_TIM7EN_Pos};
case Timer_Key::S_TIM14: return {&RCC->APB1ENR, RCC_APB1ENR_TIM14EN_Pos};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN_Pos};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN_Pos};
case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN_Pos};
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
@@ -52,6 +56,8 @@ constexpr volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
case Timer_Key::S_TIM1: return TIM1;
case Timer_Key::S_TIM2: return TIM2;
case Timer_Key::S_TIM3: return TIM3;
case Timer_Key::S_TIM6: return TIM6;
case Timer_Key::S_TIM7: return TIM7;
case Timer_Key::S_TIM14: return TIM14;
case Timer_Key::S_TIM15: return TIM15;
case Timer_Key::S_TIM16: return TIM16;
@@ -69,6 +75,8 @@ constexpr IRQn_Type getIRQn(Timer_Key t) {
case Timer_Key::S_TIM1: return TIM1_BRK_UP_TRG_COM_IRQn;
case Timer_Key::S_TIM2: return TIM2_IRQn;
case Timer_Key::S_TIM3: return TIM3_IRQn;
case Timer_Key::S_TIM6: return TIM6_DAC_IRQn;
case Timer_Key::S_TIM7: return TIM7_IRQn;
case Timer_Key::S_TIM14: return TIM14_IRQn;
case Timer_Key::S_TIM15: return TIM15_IRQn;
case Timer_Key::S_TIM16: return TIM16_IRQn;

2
SHAL/Src/Peripheral/Timer/Reg/SHAL_TIM.cpp
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@@ -7,7 +7,7 @@
Timer::Timer(Timer_Key t) : timer(t), timer_reg(getTimerRegister(t)){
SHAL_Peripheral rcc = getTimerRCC(timer);
*rcc.reg |= rcc.bitmask;
*rcc.reg |= (1 << rcc.offset);
}
Timer::Timer() : timer(Timer_Key::S_TIM_INVALID), timer_reg(nullptr){

2
SHAL/Src/main.cpp
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@@ -19,7 +19,7 @@ int main() {
Timer timer2 = getTimer(Timer_Key::S_TIM2);
timer2.setPrescaler(8000 - 1);
timer2.setARR(500 - 1);
timer2.setARR(1500 - 1);
timer2.setCallbackFunc(tim2Handler);
timer2.start();