lucalizaranzu/Shmingo-HAL
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Major refactor for entire system - wrong branch but get over it

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Ea-r-th
2025-09-10 01:20:50 -07:00
parent 316edd32d8
commit 2f8ba8d9ee
8 changed files with 106 additions and 111 deletions
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21
SHAL/Src/Peripheral/UART/SHAL_UART.cpp
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@@ -17,24 +17,11 @@ UART::UART(const UART_Pair pair) : m_UARTPair(pair){
GPIO_Key Tx_Key = uart_pair.TxKey; //Tx pin
GPIO_Key Rx_Key = uart_pair.RxKey; //Rx pin
uint8_t Tx_Pin = getGPIORegister(Tx_Key).global_offset;
uint8_t Rx_Pin = getGPIORegister(Rx_Key).global_offset;
GET_GPIO(Tx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
GET_GPIO(Rx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
initGPIO(Tx_Key,PinMode::ALTERNATE_FUNCTION_MODE); //Initialize Tx GPIO with alternate function (initializes GPIO port as well)
initGPIO(Rx_Key,PinMode::ALTERNATE_FUNCTION_MODE); //Initialize Rx GPIO with alternate function
//Determine which AFR register (high or low) to write depending on pin
uint8_t TxAFR = Tx_Pin < 8 ? 0 : 1; //Use AFR[0] if pin < 8, AFR[1] if pin >= 8
uint8_t RxAFR = Rx_Pin < 8 ? 0 : 1;
/*Apply Alternate Function masks to the AFR registers for each GPIO to enable alternate functions
* The AFR register for GPIO_Typedef* is actually two registers - a low reg and high reg.
* The low reg handles pins 0-7, and the high reg handles 8-15.
* Each pin gets 4 bits in the register for AFR0 - AFR7. Hence 8 * 4 = 32 bits.
* Each AFR is a different function, look at the DATASHEET (not reference manual) to find these alternate function mappings
*/
getGPIORegister(Tx_Key).reg->AFR[TxAFR] |= getAFMask(uart_pair.TxMask) << (4 * (Tx_Pin % 8));
getGPIORegister(Rx_Key).reg->AFR[RxAFR] |= getAFMask(uart_pair.RxMask) << (4 * (Rx_Pin % 8));
GET_GPIO(Tx_Key).setAlternateFunction(uart_pair.TxAlternateFunctionMask);
GET_GPIO(Rx_Key).setAlternateFunction(uart_pair.RxAlternateFunctionMask);
SHAL_UART_ENABLE_REG pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the UART channel