From a0ef9c8b3277fd9b25c9204897e568d250c45a6a Mon Sep 17 00:00:00 2001 From: Luca Date: Sat, 6 Sep 2025 20:55:25 -0700 Subject: [PATCH] Added more enums handling UART/USART functionality --- CMakeLists.txt | 1 + .../Peripheral/GPIO/Reg/SHAL_GPIO_REG.h | 63 +++++++++++-------- .../GPIO/Reg/SHAL_GPIO_REG_F072xB.h | 27 +++++++- .../Peripheral/GPIO/Reg/SHAL_GPIO_TYPES.h | 39 ++++++++++++ SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h | 11 +--- SHAL/Include/Peripheral/GPIO/UART/SHAL_UART.h | 20 ++++++ 6 files changed, 124 insertions(+), 37 deletions(-) create mode 100644 SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_TYPES.h create mode 100644 SHAL/Include/Peripheral/GPIO/UART/SHAL_UART.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 8d78d5e..c6ad0ac 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -34,6 +34,7 @@ set(PROJECT_INCLUDE_DIRECTORIES SHAL/Include/Peripheral/Timer/Reg SHAL/Include/Peripheral/GPIO SHAL/Include/Peripheral/GPIO/Reg + SHAL/Include/Peripheral/GPIO/UART SHAL/Include/Peripheral/EXT/ ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include ) diff --git a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h index 144000f..2e6cce8 100644 --- a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h +++ b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h @@ -5,34 +5,43 @@ #ifndef SHMINGO_HAL_SHAL_GPIO_REG_H #define SHMINGO_HAL_SHAL_GPIO_REG_H -#include "SHAL_CORE.h" +#if defined(STM32F030x6) +#include "stm32f030x6.h" +#elif defined(STM32F030x8) +#include "stm32f030x8.h" +#elif defined(STM32F031x6) +#include "stm32f031x6.h" +#elif defined(STM32F038xx) +#include "stm32f038xx.h" +#elif defined(STM32F042x6) +#include "stm32f042x6.h" +#elif defined(STM32F048xx) +#include "stm32f048xx.h" +#elif defined(STM32F051x8) +#include "stm32f051x8.h" +#elif defined(STM32F058xx) +#include "stm32f058xx.h" +#elif defined(STM32F070x6) +#include "stm32f070x6.h" +#elif defined(STM32F070xB) +#include "stm32f070xb.h" +#elif defined(STM32F071xB) +#include "stm32f071xb.h" +#elif defined(STM32F072xB) +#include "stm32f072xb.h" +#include "SHAL_GPIO_REG_F072xB.h" +#elif defined(STM32F078xx) +#include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif -struct SHAL_EXTIO_Register{ - volatile uint32_t* EXT_ICR; - uint32_t mask; - IRQn_Type IRQN; -}; - -enum class AF_Mask : uint8_t{ - AF0 = 0x00, - AF1 = 0x01, - AF2 = 0x02, - AF3 = 0x03, - AF4 = 0x04, - AF5 = 0x05, - AF6 = 0x06, - AF7 = 0x07 -}; - -//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping -struct SHAL_UART_Pair{ - uint8_t TxPinNumber; - uint8_t RxPinNumber; - volatile uint32_t* TxReg; - volatile uint32_t* RxReg; - AF_Mask TxMask; - AF_Mask RxMask; -}; diff --git a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h index 7e4b43f..3e67aa3 100644 --- a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h +++ b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h @@ -8,7 +8,7 @@ #include #include -#include "SHAL_GPIO_REG.h" +#include "SHAL_GPIO_TYPES.h" #define AVAILABLE_PORTS 3 #define PINS_PER_PORT 16 @@ -49,6 +49,13 @@ enum class UART_Pair : uint8_t{ Tx4C10_Rx4C11 }; +enum class USART { + USART_1, + USART_2, + USART_3, + USART_4 +}; + constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){ switch(pair){ case UART_Pair::Tx1A9_Rx1A10: return {9,10,&GPIOA->AFR[1],&GPIOA->AFR[1],AF_Mask::AF1,AF_Mask::AF1}; @@ -63,6 +70,24 @@ constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){ } } +constexpr USART getUSARTReg(const UART_Pair pair){ + switch(pair){ + case UART_Pair::Tx1A9_Rx1A10: + case UART_Pair::Tx1B6_Rx1B7: + return USART::USART_1; + case UART_Pair::Tx2A2_Rx2A3: + case UART_Pair::Tx2A14_Rx2A15: + return USART::USART_2; + case UART_Pair::Tx3B10_Rx3B11: + case UART_Pair::Tx3C4_Rx3C5: + case UART_Pair::Tx3C10_Rx3C11: + return USART::USART_3; + case UART_Pair::Tx4A0_Rx4A1: + case UART_Pair::Tx4C10_Rx4C11: + return USART::USART_4; + } +} + constexpr SHAL_Peripheral getGPIORegister(const GPIO_Key g){ switch(g) { diff --git a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_TYPES.h b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_TYPES.h new file mode 100644 index 0000000..4469e88 --- /dev/null +++ b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_TYPES.h @@ -0,0 +1,39 @@ +// +// Created by Luca on 9/6/2025. +// + +#ifndef SHMINGO_HAL_SHAL_GPIO_TYPES_H +#define SHMINGO_HAL_SHAL_GPIO_TYPES_H + +#include "SHAL_CORE.h" + + +struct SHAL_EXTIO_Register{ + volatile uint32_t* EXT_ICR; + uint32_t mask; + IRQn_Type IRQN; +}; + +enum class AF_Mask : uint8_t{ + AF0 = 0x00, + AF1 = 0x01, + AF2 = 0x02, + AF3 = 0x03, + AF4 = 0x04, + AF5 = 0x05, + AF6 = 0x06, + AF7 = 0x07 +}; + +//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping +struct SHAL_UART_Pair{ + + uint8_t TxPinNumber; + uint8_t RxPinNumber; + volatile uint32_t* TxReg; + volatile uint32_t* RxReg; + AF_Mask TxMask; + AF_Mask RxMask; +}; + +#endif //SHMINGO_HAL_SHAL_GPIO_TYPES_H diff --git a/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h b/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h index 2d32af9..7925774 100644 --- a/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h +++ b/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h @@ -5,10 +5,10 @@ #ifndef SHMINGO_HAL_SHAL_GPIO_H #define SHMINGO_HAL_SHAL_GPIO_H -#include "SHAL_CORE.h" +#include "SHAL_GPIO_REG.h" #include -#include "SHAL_GPIO_REG_F072xB.h" + #include "SHAL_EXTI_CALLBACK.h" @@ -28,13 +28,6 @@ enum class TriggerMode : uint8_t{ RISING_FALLING_EDGE }; -unsigned long getTriggerMode(TriggerMode mode); - - - - - - //Abstraction of GPIO registers class GPIO{ diff --git a/SHAL/Include/Peripheral/GPIO/UART/SHAL_UART.h b/SHAL/Include/Peripheral/GPIO/UART/SHAL_UART.h new file mode 100644 index 0000000..8a69a6a --- /dev/null +++ b/SHAL/Include/Peripheral/GPIO/UART/SHAL_UART.h @@ -0,0 +1,20 @@ +// +// Created by Luca on 9/6/2025. +// + +#ifndef SHMINGO_HAL_SHAL_UART_H +#define SHMINGO_HAL_SHAL_UART_H + +#include "SHAL_GPIO_REG.h" + +class UART{ + +public: + +private: + + + +}; + +#endif //SHMINGO_HAL_SHAL_UART_H