ADC sequence abstracted
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@@ -11,6 +11,32 @@
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#define SHAL_ADC1 SHAL_ADC(1)
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#define NUM_ADCS 1
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#define NUM_ADC_CHANNELS 16
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enum class SHAL_ADC_Channel : uint32_t {
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CH0,
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CH1,
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CH2,
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CH3,
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CH4,
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CH5,
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CH6,
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CH7,
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CH8,
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CH9,
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CH10,
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CH11,
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CH12,
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CH13,
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CH14,
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CH15,
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CHTemp,
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CHRef,
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CHBat
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};
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enum class ADC_Key : uint8_t{
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S_ADC1 = 0,
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NUM_ADC = 1,
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@@ -89,7 +115,7 @@ SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key
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volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
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volatile uint32_t* SMPReg = nullptr;
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uint32_t pos = 0;
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uint32_t pos;
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auto channelNum = static_cast<uint8_t>(channel);
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@@ -104,6 +130,34 @@ SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key
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return {SMPReg, pos};
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}
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SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
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SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
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res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
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return res;
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}
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SHAL_ADC_Sequence_Reg getADCSequenceRegisters(ADC_Key key){
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volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];
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SHAL_ADC_Sequence_Reg res = {{&adc_reg->SQR1,
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&adc_reg->SQR2,
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&adc_reg->SQR3,
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&adc_reg->SQR4,
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nullptr,
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nullptr},
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{1UL << 0,
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1UL << 6,
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1UL << 12,
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1UL << 18,
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1UL << 24}
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};
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return res;
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}
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constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
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switch(key){
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case ADC_Key::S_ADC1:
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