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Beginning of cross platform support

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This commit is contained in:
Ea-r-th
2025-10-08 23:37:10 -07:00
parent ece09aad0b
commit c76dbee94c
85 changed files with 20857 additions and 17 deletions
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51
SHAL/Include/Core/SHAL_CORE.h
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@@ -101,10 +101,59 @@ bool SHAL_wait_for_condition_ms(Condition cond, uint32_t timeout_ms) {
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#error "Please select first the target STM32 device used in your application (in stm32f0xx.h file)"
#endif

31
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_L432KC.h Normal file
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@@ -0,0 +1,31 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_REG_L432KC_H
#define SHMINGO_HAL_SHAL_ADC_REG_L432KC_H
#include "SHAL_CORE.h"
#include "SHAL_ADC_TYPES.h"
#define SHAL_ADC1 SHAL_ADC(1)
enum class ADC_Key : uint8_t{
S_ADC1,
NUM_ADC,
INVALID
};
constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
switch(key){
case ADC_Key::S_ADC1:
return ADC1;
case ADC_Key::NUM_ADC:
case ADC_Key::INVALID:
return nullptr;
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_ADC_REG_L432KC_H

51
SHAL/Include/Peripheral/ADC/SHAL_ADC_REG.h
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@@ -37,6 +37,57 @@
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_ADC_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

12
SHAL/Include/Peripheral/EXT/Reg/SHAL_EXTI_REG_F072xB.h Normal file
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@@ -0,0 +1,12 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_EXTI_REG_F072XB_H
#define SHMINGO_HAL_SHAL_EXTI_REG_F072XB_H
#include "SHAL_CORE.h"
#define EXTI_PENDING_REG(line) (EXTI->PR)
#endif //SHMINGO_HAL_SHAL_EXTI_REG_F072XB_H

12
SHAL/Include/Peripheral/EXT/Reg/SHAL_EXTI_REG_L432KC.h Normal file
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@@ -0,0 +1,12 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H
#define SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H
#include "SHAL_CORE.h"
#define EXTI_PENDING_REG(line) ((line) < 32 ? EXTI->PR1 : EXTI->PR2)
#endif //SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H

9
SHAL/Include/Peripheral/EXT/SHAL_EXTI_CALLBACK.h
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@@ -11,11 +11,12 @@
#include "SHAL_CORE.h"
#include "SHAL_GPIO_REG.h"
#include "SHAL_EXTI_REG.h"
#define DEFINE_EXTI_IRQ(EXTI_Channel) \
extern "C" void EXTI##EXTI_Channel##_IRQHandler(void) { \
if (EXTI->PR & (1 << EXTI_Channel)) { \
EXTI->PR |= (1 << EXTI_Channel); /*clear flag */ \
if (EXTI_PENDING_REG(EXTI_Channel) & (1 << EXTI_Channel)) { \
EXTI_PENDING_REG(EXTI_Channel) |= (1 << EXTI_Channel); /*clear flag */ \
auto cb = EXTI_callbacks[EXTI_Channel]; \
if (cb) cb(); \
}; \
@@ -24,8 +25,8 @@ extern "C" void EXTI##EXTI_Channel##_IRQHandler(void) { \
#define DEFINE_MULTI_EXTI_IRQ(EXTI_Channel_Min, EXTI_Channel_Max) \
extern "C" void EXTI##EXTI_Channel_Min##_##EXTI_Channel_Max##_IRQHandler(void) { \
for(uint8_t line = EXTI_Channel_Min; line <= EXTI_Channel_Max; line++){ \
if (EXTI->PR & (1 << line)) { \
EXTI->PR |= (1 << line); /*clear flag */ \
if (EXTI_PENDING_REG(EXTI_Channel_Max) & (1 << line)) { \
EXTI_PENDING_REG(EXTI_Channel_Max) |= (1 << line); /*clear flag */ \
auto cb = EXTI_callbacks[line]; \
if (cb) cb(); \
}; \

100
SHAL/Include/Peripheral/EXT/SHAL_EXTI_REG.h Normal file
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@@ -0,0 +1,100 @@
//
// Created by Luca on 9/6/2025.
//
#ifndef SHAL_EXTI_REG_H
#define SHAL_EXTI_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_EXTI_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_EXTI_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHAL_EXTI_REG_H

4
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h
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@@ -89,7 +89,7 @@ constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
__builtin_unreachable();
}
constexpr SHAL_EXTIO_Register getGPIOEXTICR(const GPIO_Key g){
constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PA,EXTI0_1_IRQn};
case GPIO_Key::A1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PA,EXTI0_1_IRQn};
@@ -143,7 +143,7 @@ constexpr SHAL_EXTIO_Register getGPIOEXTICR(const GPIO_Key g){
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_EXTIO_Register(nullptr,0, EXTI4_15_IRQn); //Unreachable
return SHAL_GPIO_EXTI_Register(nullptr, 0, EXTI4_15_IRQn); //Unreachable
}
__builtin_unreachable();
}

325
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_L432KC.h Normal file
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@@ -0,0 +1,325 @@
//
// Created by Luca on 8/29/2025.
//
#ifndef SHAL_GPIO_REG_F072XB_H
#define SHAL_GPIO_REG_F072XB_H
#include <stm32l432xx.h>
#include <cassert>
#include "SHAL_GPIO_TYPES.h"
#define AVAILABLE_PORTS 3
#define PINS_PER_PORT 16
#define NUM_EXTI_LINES 16
#define AVAILABLE_GPIO \
X(A0) X(A1) X(A2) X(A3) X(A4) X(A5) X(A6) X(A7) X(A8) X(A9) X(A10) X(A11) X(A12) X(A13) X(A14) X(A15) \
X(B0) X(B1) X(B2) X(B3) X(B4) X(B5) X(B6) X(B7) X(B8) X(B9) X(B10) X(B11) X(B12) X(B13) X(B14) X(B15) \
X(C0) X(C1) X(C2) X(C3) X(C4) X(C5) X(C6) X(C7) X(C8) X(C9) X(C10) X(C11) X(C12) X(C13) X(C14) X(C15)
//Build enum map of available SHAL_GPIO pins
enum class GPIO_Key : uint8_t {
#define X(key) key,
AVAILABLE_GPIO
#undef X
NUM_GPIO,
INVALID
};
constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {GPIOA,0};
case GPIO_Key::A1: return {GPIOA,1};
case GPIO_Key::A2: return {GPIOA,2};
case GPIO_Key::A3: return {GPIOA,3};
case GPIO_Key::A4: return {GPIOA,4};
case GPIO_Key::A5: return {GPIOA,5};
case GPIO_Key::A6: return {GPIOA,6};
case GPIO_Key::A7: return {GPIOA,7};
case GPIO_Key::A8: return {GPIOA,8};
case GPIO_Key::A9: return {GPIOA,9};
case GPIO_Key::A10: return {GPIOA,10};
case GPIO_Key::A11: return {GPIOA,11};
case GPIO_Key::A12: return {GPIOA,12};
case GPIO_Key::A13: return {GPIOA,13};
case GPIO_Key::A14: return {GPIOA,14};
case GPIO_Key::A15: return {GPIOA,15};
case GPIO_Key::B0: return {GPIOB,0};
case GPIO_Key::B1: return {GPIOB,1};
case GPIO_Key::B2: return {GPIOB,2};
case GPIO_Key::B3: return {GPIOB,3};
case GPIO_Key::B4: return {GPIOB,4};
case GPIO_Key::B5: return {GPIOB,5};
case GPIO_Key::B6: return {GPIOB,6};
case GPIO_Key::B7: return {GPIOB,7};
case GPIO_Key::B8: return {GPIOB,8};
case GPIO_Key::B9: return {GPIOB,9};
case GPIO_Key::B10: return {GPIOB,10};
case GPIO_Key::B11: return {GPIOB,11};
case GPIO_Key::B12: return {GPIOB,12};
case GPIO_Key::B13: return {GPIOB,13};
case GPIO_Key::B14: return {GPIOB,14};
case GPIO_Key::B15: return {GPIOB,15};
case GPIO_Key::C0: return {GPIOC,0};
case GPIO_Key::C1: return {GPIOC,1};
case GPIO_Key::C2: return {GPIOC,2};
case GPIO_Key::C3: return {GPIOC,3};
case GPIO_Key::C4: return {GPIOC,4};
case GPIO_Key::C5: return {GPIOC,5};
case GPIO_Key::C6: return {GPIOC,6};
case GPIO_Key::C7: return {GPIOC,7};
case GPIO_Key::C8: return {GPIOC,8};
case GPIO_Key::C9: return {GPIOC,9};
case GPIO_Key::C10: return {GPIOC,10};
case GPIO_Key::C11: return {GPIOC,11};
case GPIO_Key::C12: return {GPIOC,12};
case GPIO_Key::C13: return {GPIOC,13};
case GPIO_Key::C14: return {GPIOC,14};
case GPIO_Key::C15: return {GPIOC,15};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_GPIO_Peripheral(nullptr,0); //Unreachable
}
__builtin_unreachable();
}
constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PA,EXTI0_IRQn};
case GPIO_Key::A1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PA,EXTI1_IRQn};
case GPIO_Key::A2: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI2_PA,EXTI2_IRQn};
case GPIO_Key::A3: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI3_PA,EXTI3_IRQn};
case GPIO_Key::A4: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI4_PA,EXTI4_IRQn};
case GPIO_Key::A5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PA,EXTI9_5_IRQn};
case GPIO_Key::A6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PA,EXTI9_5_IRQn};
case GPIO_Key::A7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PA,EXTI9_5_IRQn};
case GPIO_Key::A8: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI8_PA,EXTI9_5_IRQn};
case GPIO_Key::A9: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI9_PA,EXTI9_5_IRQn};
case GPIO_Key::A10: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI10_PA,EXTI15_10_IRQn};
case GPIO_Key::A11: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI11_PA,EXTI15_10_IRQn};
case GPIO_Key::A12: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI12_PA,EXTI15_10_IRQn};
case GPIO_Key::A13: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI13_PA,EXTI15_10_IRQn};
case GPIO_Key::A14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PA,EXTI15_10_IRQn};
case GPIO_Key::A15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PA,EXTI15_10_IRQn};
case GPIO_Key::B0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PB,EXTI0_IRQn};
case GPIO_Key::B1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PB,EXTI1_IRQn};
case GPIO_Key::B3: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI3_PB,EXTI3_IRQn};
case GPIO_Key::B4: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI4_PB,EXTI4_IRQn};
case GPIO_Key::B5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PB,EXTI9_5_IRQn};
case GPIO_Key::B6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PB,EXTI9_5_IRQn};
case GPIO_Key::B7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PB,EXTI9_5_IRQn};
case GPIO_Key::C14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PC,EXTI15_10_IRQn};
case GPIO_Key::C15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PC,EXTI15_10_IRQn};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_GPIO_EXTI_Register(nullptr, 0, static_cast<IRQn_Type>(0)); //Unreachable
}
__builtin_unreachable();
}
constexpr SHAL_Peripheral_Register getGPIORCCEnable(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN_Pos};
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN_Pos};
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN_Pos};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_Peripheral_Register(nullptr,0); //Unreachable
}
__builtin_unreachable();
}
constexpr uint32_t getGPIOPortNumber(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return 0;
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return 1;
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return 2;
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return 0;
}
__builtin_unreachable();
}
constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
switch(key){
case GPIO_Key::A0:
case GPIO_Key::B0:
case GPIO_Key::C0:
return {0,ADC_Channel::CH0};
case GPIO_Key::A1:
case GPIO_Key::B1:
case GPIO_Key::C1:
return {1,ADC_Channel::CH1};
case GPIO_Key::A2:
case GPIO_Key::B2:
case GPIO_Key::C2:
return {2,ADC_Channel::CH2};
case GPIO_Key::A3:
case GPIO_Key::B3:
case GPIO_Key::C3:
return {3,ADC_Channel::CH3};
case GPIO_Key::A4:
case GPIO_Key::B4:
case GPIO_Key::C4:
return {4,ADC_Channel::CH4};
case GPIO_Key::A5:
case GPIO_Key::B5:
case GPIO_Key::C5:
return {5,ADC_Channel::CH5};
case GPIO_Key::A6:
case GPIO_Key::B6:
case GPIO_Key::C6:
return {6,ADC_Channel::CH6};
case GPIO_Key::A7:
case GPIO_Key::B7:
case GPIO_Key::C7:
return {7,ADC_Channel::CH7};
case GPIO_Key::A8:
case GPIO_Key::B8:
case GPIO_Key::C8:
return {8,ADC_Channel::CH8};
case GPIO_Key::A9:
case GPIO_Key::B9:
case GPIO_Key::C9:
return {9,ADC_Channel::CH9};
case GPIO_Key::A10:
case GPIO_Key::B10:
case GPIO_Key::C10:
return {10,ADC_Channel::CH10};
case GPIO_Key::A11:
case GPIO_Key::B11:
case GPIO_Key::C11:
return {11,ADC_Channel::CH11};
case GPIO_Key::A12:
case GPIO_Key::B12:
case GPIO_Key::C12:
return {12,ADC_Channel::CH12};
case GPIO_Key::A13:
case GPIO_Key::B13:
case GPIO_Key::C13:
return {13,ADC_Channel::CH13};
case GPIO_Key::A14:
case GPIO_Key::B14:
case GPIO_Key::C14:
return {14,ADC_Channel::CH14};
case GPIO_Key::A15:
case GPIO_Key::B15:
case GPIO_Key::C15:
return {15,ADC_Channel::CH15};
case GPIO_Key::NUM_GPIO:
case GPIO_Key::INVALID:
return {0,ADC_Channel::CH0};
}
__builtin_unreachable();
}
#endif //SHAL_GPIO_REG_F072XB_H

53
SHAL/Include/Peripheral/GPIO/SHAL_GPIO_REG.h
View File

@@ -37,7 +37,60 @@
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_GPIO_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

9
SHAL/Include/Peripheral/GPIO/SHAL_GPIO_TYPES.h
View File

@@ -7,11 +7,12 @@
#include "SHAL_CORE.h"
#include "SHAL_ADC.h"
#include "SHAL_ADC_TYPES.h"
struct SHAL_EXTIO_Register{
volatile uint32_t* EXT_ICR;
uint32_t mask;
IRQn_Type IRQN;
struct SHAL_GPIO_EXTI_Register{
volatile uint32_t* EXT_ICR; //4 32 bit registers which say which GPIO a line is connected to
uint32_t mask; //Mask for enabling GPIO connection
IRQn_Type IRQN; //IRQ number for enabling lines
};
struct SHAL_GPIO_Peripheral {

81
SHAL/Include/Peripheral/I2C/Reg/SHAL_I2C_REG_L432KC.h Normal file
View File

@@ -0,0 +1,81 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_I2C_REG_L432KC_H
#define SHMINGO_HAL_SHAL_I2C_REG_L432KC_H
#include "SHAL_CORE.h"
#include "SHAL_I2C_TYPES.h"
enum class I2C_Pair : uint8_t{
//I2C_1
SCL1A9_SDA1A10, //AF4
SCL1B6_SDA1B7, //AF4
//I2C_3
SCL3A7_SDA3B4, //AF4
NUM_PAIRS,
INVALID
};
constexpr SHAL_I2C_Pair getI2CPair(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10: return {I2C1,GPIO_Key::A9,GPIO_Key::A10,GPIO_Alternate_Function::AF4,GPIO_Alternate_Function::AF4};
case I2C_Pair::SCL1B6_SDA1B7: return {I2C1,GPIO_Key::B6,GPIO_Key::B7,GPIO_Alternate_Function::AF4,GPIO_Alternate_Function::AF4};
case I2C_Pair::SCL3A7_SDA3B4: return {I2C3,GPIO_Key::A7,GPIO_Key::B4,GPIO_Alternate_Function::AF4,GPIO_Alternate_Function::AF4};
case I2C_Pair::INVALID:
assert(false);
return {nullptr,GPIO_Key::INVALID,GPIO_Key::INVALID,GPIO_Alternate_Function::AF0,GPIO_Alternate_Function::AF0};
}
__builtin_unreachable();
}
constexpr SHAL_I2C_Enable_Reg getI2CEnableReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10:
case I2C_Pair::SCL1B6_SDA1B7:
return {&RCC->APB1ENR1,RCC_APB1ENR1_I2C1EN};
case I2C_Pair::SCL3A7_SDA3B4:
return {&RCC->APB1ENR1,RCC_APB1ENR1_I2C3EN};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
constexpr SHAL_I2C_Reset_Reg getI2CResetReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10:
case I2C_Pair::SCL1B6_SDA1B7:
return {&RCC->APB1RSTR1,RCC_APB1RSTR1_I2C1RST};
case I2C_Pair::SCL3A7_SDA3B4:
return {&RCC->APB1RSTR1,RCC_APB1RSTR1_I2C3RST};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
//Gets all the bits in the I2C timer register, these values should rarely be manually set, but I wanted to support it anyway
constexpr SHAL_I2C_Timing_Reg getI2CTimerReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10:
case I2C_Pair::SCL1B6_SDA1B7:
return {&I2C1->TIMINGR,31,23,19,15,7};
case I2C_Pair::SCL3A7_SDA3B4:
return {&I2C3->TIMINGR,31,23,19,15,7};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
__builtin_unreachable();
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_I2C_REG_L432KC_H

51
SHAL/Include/Peripheral/I2C/SHAL_I2C_REG.h
View File

@@ -37,8 +37,57 @@
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#error "Please select first the target STM32 device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHAL_I2C_REG_H

51
SHAL/Include/Peripheral/Timer/SHAL_TIM_REG.h
View File

@@ -37,6 +37,57 @@
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

51
SHAL/Include/Peripheral/UART/SHAL_UART_REG.h
View File

@@ -38,6 +38,57 @@
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

0
SHAL/Src/Core/SHAL_CORE.cpp → SHAL/Src/STM32F0XX/Core/SHAL_CORE.cpp
View File

0
SHAL/Src/EXT/SHAL_EXTI_CALLBACK.cpp → SHAL/Src/STM32F0XX/EXT/SHAL_EXTI_CALLBACK.cpp
View File

0
SHAL/Src/Peripheral/ADC/SHAL_ADC.cpp → SHAL/Src/STM32F0XX/Peripheral/ADC/SHAL_ADC.cpp
View File

0
SHAL/Src/Peripheral/GPIO/SHAL_GPIO.cpp → SHAL/Src/STM32F0XX/Peripheral/GPIO/SHAL_GPIO.cpp
View File

0
SHAL/Src/Peripheral/I2C/SHAL_I2C.cpp → SHAL/Src/STM32F0XX/Peripheral/I2C/SHAL_I2C.cpp
View File

0
SHAL/Src/Peripheral/Timer/SHAL_TIM.cpp → SHAL/Src/STM32F0XX/Peripheral/Timer/SHAL_TIM.cpp
View File

0
SHAL/Src/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp → SHAL/Src/STM32F0XX/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp
View File

0
SHAL/Src/Peripheral/UART/SHAL_UART.cpp → SHAL/Src/STM32F0XX/Peripheral/UART/SHAL_UART.cpp
View File

0
SHAL/Src/System/system_stm32f0xx.c → SHAL/Src/STM32F0XX/System/system_stm32f0xx.c
View File

42
SHAL/Src/STM32L4XX/Core/SHAL_CORE.cpp Normal file
View File

@@ -0,0 +1,42 @@
//
// Created by Luca on 9/15/2025.
//
#include "SHAL_CORE.h"
void SHAL_init(){
systick_init(); //Just this for now
}
void systick_init(){
SysTick->CTRL = 0; //Disable first
SysTick->LOAD = 0xFFFFFF; //Max 24-bit
SysTick->VAL = 0; //Clear
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
}
void SHAL_delay_us(uint32_t us){
uint32_t ticks = us * (SystemCoreClock / 1000000U);
uint32_t start = SysTick->VAL;
//Calculate target value (may wrap around)
uint32_t target = (start >= ticks) ? (start - ticks) : (start + 0x01000000 - ticks);
target &= 0x00FFFFFF;
//Wait until we reach the target
if (start >= ticks) {
//No wraparound case
while (SysTick->VAL > target) {}
} else {
while (SysTick->VAL <= start) {} //Wait for wraparound
while (SysTick->VAL > target) {} //Wait for target
}
}
void SHAL_delay_ms(uint32_t ms){
while(ms-- > 0){
SHAL_delay_us(1000);
}
}

41
SHAL/Src/STM32L4XX/EXT/SHAL_EXTI_CALLBACK.cpp Normal file
View File

@@ -0,0 +1,41 @@
//
// Created by Luca on 9/3/2025.
//
#include "SHAL_EXTI_CALLBACK.h"
#if defined(STM32L412xx)
#elif defined(STM32L422xx)
#elif defined(STM32L431xx)
#elif defined(STM32L432xx)
DEFINE_EXTI_IRQ()
#elif defined(STM32L433xx)
#elif defined(STM32L442xx)
#elif defined(STM32L443xx)
#elif defined(STM32L451xx)
#elif defined(STM32L452xx)
#elif defined(STM32L462xx)
#elif defined(STM32L471xx)
#elif defined(STM32L475xx)
#elif defined(STM32L476xx)
#elif defined(STM32L485xx)
#elif defined(STM32L486xx)
#elif defined(STM32L496xx)
#elif defined(STM32L4A6xx)
#elif defined(STM32L4P5xx)
#elif defined(STM32L4Q5xx)
#elif defined(STM32L4R5xx)
#elif defined(STM32L4R7xx)
#elif defined(STM32L4R9xx)
#elif defined(STM32L4S5xx)
#elif defined(STM32L4S7xx)
#elif defined(STM32L4S9xx)
#error "Please select first the target STM32L4xx device used in your application (in stm32f0xx.h file)"
#endif
//Link function to EXTI line
void registerEXTICallback(GPIO_Key key, EXTICallback callback){
EXTI_callbacks[getGPIORegister(key).global_offset] = callback;
}

115
SHAL/Src/STM32L4XX/Peripheral/ADC/SHAL_ADC.cpp Normal file
View File

@@ -0,0 +1,115 @@
//
// Created by Luca on 9/21/2025.
//
#include "SHAL_ADC.h"
//Can hard code registers on F0 because all F0 devices have only one ADC, and use only one clock
SHAL_Result SHAL_ADC::init() {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return SHAL_Result::ERROR;
}
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; //Enable clock
RCC->CR2 |= RCC_CR2_HSI14ON; //Start peripheral oscillator
if(!SHAL_WAIT_FOR_CONDITION_US(((RCC->CR2 & RCC_CR2_HSI14RDY) != 0),50)){ //Wait for clock OKAY
return SHAL_Result::ERROR;
}
if((ADC_reg->ISR & ADC_ISR_ADRDY) != 0){ //Set ADRDY to 0
ADC_reg->ISR |= ADC_ISR_ADRDY;
}
ADC_reg->CR |= ADC_CR_ADEN; //Enable
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_ADRDY) != 0),50)){ //Wait for disable
return SHAL_Result::ERROR;
}
if(calibrate() != SHAL_Result::OKAY){ //Calibrate
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::calibrate() {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return SHAL_Result::ERROR;
}
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
if((ADC_reg->CR & ADC_CR_ADEN) != 0){ //Clear ADEN (enable)
ADC_reg->CR |= ADC_CR_ADDIS;
}
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->CR & ADC_CR_ADEN) == 0),50)){ //Wait for disable
return SHAL_Result::ERROR;
}
ADC_reg->CFGR1 &= ~ADC_CFGR1_DMAEN; //Clear DMAEN
ADC_reg->CR |= ADC_CR_ADCAL; //Launch calibration by setting ADCAL
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->CR & ADC_CR_ADCAL) == 0),50)){ //Wait for calibration
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
uint16_t SHAL_ADC::singleConvertSingle(ADC_Channel channel, ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_TSEN; //Enable VREFINT and Temp sensor in global ADC struct
ADC_reg->CHSELR = static_cast<uint32_t>(channel); //Enable channel for conversion
ADC_reg->SMPR |= static_cast<uint32_t>(time); //Set sampling time
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_EOC) != 0),500)){ //Wait for conversion
return 0; //Failed
}
uint16_t result = ADC_reg->DR;
return result;
}
void SHAL_ADC::multiConvertSingle(ADC_Channel* channels, const int numChannels, uint16_t* result, ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_TSEN; //Enable VREFINT and Temp sensor in global ADC struct
for(int i = 0; i < numChannels; i++){ //Enable all channels
ADC_reg->CHSELR = static_cast<uint32_t>(channels[i]);
}
ADC_reg->SMPR |= static_cast<uint32_t>(time); //Set sampling time
for(int i = 0; i < numChannels; i++){
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_EOC) != 0),500)){ //Wait for conversion
continue; //Failed
}
result[i] = ADC_reg->DR;
}
}
SHAL_ADC &ADCManager::get(ADC_Key key) {
return m_ADCs[static_cast<uint8_t>(key)];
}
SHAL_ADC& ADCManager::getByIndex(int index) {
if(index < static_cast<int>(ADC_Key::NUM_ADC)){
return m_ADCs[index];
}
return m_ADCs[0];
}

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//
// Created by Luca on 8/30/2025.
//
#include "SHAL_GPIO.h"
#include "SHAL_EXTI_CALLBACK.h"
SHAL_GPIO::SHAL_GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
volatile unsigned long* gpioEnable = getGPIORCCEnable(key).reg;
unsigned long gpioOffset = getGPIORCCEnable(key).offset;
*gpioEnable |= (1 << gpioOffset); //Set enable flag
}
void SHAL_GPIO::setLow() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR &= ~(1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setHigh() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR |= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::toggle() volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR ^= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setPinType(PinType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OTYPER &= ~(1 << gpioPeripheral.global_offset);
gpioPeripheral.reg->OTYPER |= (static_cast<uint8_t>(type) << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OSPEEDR |= (static_cast<uint8_t>(speed) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setInternalResistor(InternalResistorType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->PUPDR &= ~(0x03 << (2 * gpioPeripheral.global_offset));
gpioPeripheral.reg->PUPDR |= (static_cast<uint8_t>(type) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
int afrIndex = gpioPeripheral.global_offset < 8 ? 0 : 1; //Get index of AFR
gpioPeripheral.reg->AFR[afrIndex] &= ~(0xF << (gpioPeripheral.global_offset * 4));
gpioPeripheral.reg->AFR[afrIndex] |= (static_cast<int>(AF) << (gpioPeripheral.global_offset * 4));
}
void SHAL_GPIO::setPinMode(PinMode mode) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->MODER &= ~(0x03 << (2 * gpioPeripheral.global_offset)); //Clear any previous mode
gpioPeripheral.reg->MODER |= (static_cast<uint8_t>(mode) << (2 * gpioPeripheral.global_offset)); //Set mode based on pinmode bit structure
}
void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {
uint32_t gpioPin = getGPIORegister(m_GPIO_KEY).global_offset; //Use existing structs to get offset
setPinMode(PinMode::INPUT_MODE); //Explicitly set mode to input
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; //Enable EXT, TODO check if this is different across STM32 models
NVIC_EnableIRQ(getGPIOEXTICR(m_GPIO_KEY).IRQN); //Enable IRQN for pin
EXTI->IMR |= (1 << gpioPin); //Enable correct EXTI line
SHAL_EXTIO_Register EXTILineEnable = getGPIOEXTICR(m_GPIO_KEY);
*EXTILineEnable.EXT_ICR |= EXTILineEnable.mask; //Set bits to enable correct port on correct line TODO Find way to clear bits before
uint32_t rising_mask = 0x00;
uint32_t falling_mask = 0x00;
//Set rising and falling edge triggers based on pin offset (enabled EXTI line)
switch(mode){
case TriggerMode::RISING_EDGE:
rising_mask = 1 << gpioPin;
break;
case TriggerMode::FALLING_EDGE:
falling_mask = 1 << gpioPin;
break;
case TriggerMode::RISING_FALLING_EDGE:
falling_mask = 1 << gpioPin;
falling_mask = 1 << gpioPin;
}
//Set triggers
EXTI->RTSR |= rising_mask;
EXTI->FTSR |= falling_mask;
//Set callback
registerEXTICallback(m_GPIO_KEY,callback);
__enable_irq(); //Enable IRQ just in case
}
uint16_t SHAL_GPIO::analogRead(ADC_SampleTime sampleTime) {
ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
}
SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
unsigned int gpioPort = getGPIOPortNumber(key);
unsigned long gpioPin = getGPIORegister(key).global_offset; //Use existing structs to get offset
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
}
return m_gpios[gpioPort][gpioPin];
}

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//
// Created by Luca on 9/9/2025.
//
#include "SHAL_I2C.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART.h"
void SHAL_I2C::init(I2C_Pair pair) volatile {
m_I2CPair = pair;
SHAL_I2C_Pair I2CPair = getI2CPair(pair); //Get the I2C_PAIR information to be initialized
//Get the SHAL_GPIO pins for this SHAL_I2C setup
GPIO_Key SCL_Key = I2CPair.SCL_Key; //SCL pin
GPIO_Key SDA_Key = I2CPair.SDA_Key; //SDA pin
SHAL_I2C_Enable_Reg pairI2CEnable = getI2CEnableReg(pair); //Register and mask to enable the I2C peripheral
*pairI2CEnable.reg &= ~pairI2CEnable.mask; //Enable I2C peripheral clock
GET_GPIO(SCL_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE); //Implicitly initializes and enables GPIO bus
GET_GPIO(SDA_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
GET_GPIO(SCL_Key).setAlternateFunction(I2CPair.SCL_Mask);
GET_GPIO(SDA_Key).setAlternateFunction(I2CPair.SDA_Mask);
//These may be abstracted further to support multiple I2C configurations
GET_GPIO(SCL_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SDA_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SCL_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
GET_GPIO(SDA_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
GET_GPIO(SCL_Key).setInternalResistor(InternalResistorType::PULLUP);
GET_GPIO(SDA_Key).setInternalResistor(InternalResistorType::PULLUP);
SHAL_I2C_Reset_Reg pairI2CReset = getI2CResetReg(pair);
*pairI2CEnable.reg |= pairI2CEnable.mask; //Enable I2C peripheral clock
*pairI2CReset.reg |= pairI2CReset.mask; //Reset peripheral
*pairI2CReset.reg &= ~pairI2CReset.mask; //Reset peripheral
}
void SHAL_I2C::setClockConfig(uint8_t prescaler, uint8_t dataSetupTime, uint8_t dataHoldTime, uint8_t SCLHighPeriod, uint8_t SCLLowPeriod) {
SHAL_I2C_Timing_Reg clockReg = getI2CTimerReg(m_I2CPair);
*clockReg.reg |= (prescaler << clockReg.prescaler_offset);
*clockReg.reg |= (dataSetupTime << clockReg.dataSetupTime_offset);
*clockReg.reg |= (dataHoldTime << clockReg.dataHoldTime_offset);
*clockReg.reg |= (SCLHighPeriod << clockReg.SCLHighPeriod_offset);
*clockReg.reg |= (SCLLowPeriod << clockReg.SCLLowPeriod_offset);
getI2CPair(m_I2CPair).I2CReg->CR1 |= I2C_CR1_PE; //Enable I2C peripheral
}
void SHAL_I2C::setClockConfig(uint32_t configuration) {
*getI2CTimerReg(m_I2CPair).reg = configuration;
getI2CPair(m_I2CPair).I2CReg->CR1 |= I2C_CR1_PE; //Enable I2C peripheral
}
void SHAL_I2C::masterWriteRead(uint8_t addr,const uint8_t* writeData, size_t writeLen, uint8_t* readData, size_t readLen) {
volatile I2C_TypeDef* I2CPeripheral = getI2CPair(m_I2CPair).I2CReg;
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_BUSY) == 0, 100)){
SHAL_UART2.sendString("I2C timed out waiting for not busy\r\n");
return;
}
//Write phase
if (writeLen > 0) {
//Configure: NBYTES = wlen, write mode, START
I2CPeripheral->CR2 = (addr << 1) | (writeLen << I2C_CR2_NBYTES_Pos) | I2C_CR2_START;
for (size_t i = 0; i < writeLen; i++) {
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_TXIS) != 0, 100)){
SHAL_UART2.sendString("I2C timed out waiting for TX\r\n");
return;
}
I2CPeripheral->TXDR = writeData[i];
}
//Wait until transfer complete
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_TC) != 0, 100)){
SHAL_UART2.sendString("I2C timed out waiting for TC\r\n");
return;
}
}
//Read phase
if (readLen > 0) {
SHAL_UART2.sendString("Read initiated\r\n");
I2CPeripheral->CR2 &= ~(I2C_CR2_NBYTES | I2C_CR2_SADD | I2C_CR2_RD_WRN);
I2CPeripheral->CR2 |= (addr << 1) |
I2C_CR2_RD_WRN |
(readLen << I2C_CR2_NBYTES_Pos) |
I2C_CR2_START | I2C_CR2_AUTOEND;
for (size_t i = 0; i < readLen; i++) {
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_RXNE) != 0 , 100)){
SHAL_UART2.sendString("I2C timed out waiting for RXNE\r\n");
return;
}
SHAL_UART2.sendString("Read byte");
readData[i] = static_cast<uint8_t>(I2CPeripheral->RXDR);
}
}
else{
I2CPeripheral->CR2 |= I2C_CR2_STOP;
}
}
void SHAL_I2C::masterWrite(uint8_t addr, const uint8_t *writeData, uint8_t writeLen) {
masterWriteRead(addr,writeData,writeLen,nullptr,0);
}
void SHAL_I2C::masterRead(uint8_t addr, uint8_t *readBuffer, uint8_t bytesToRead) {
masterWriteRead(addr,nullptr,0,readBuffer,bytesToRead);
}
uint8_t SHAL_I2C::masterWriteReadByte(uint8_t addr, const uint8_t *writeData, size_t writeLen) {
uint8_t val = 0;
masterWriteRead(addr, writeData, writeLen, &val, 1);
return val;
}
SHAL_I2C& I2CManager::get(uint8_t I2CBus) {
if(I2CBus > NUM_I2C_BUSES - 1){
assert(false);
//Memory fault
}
return m_I2CBuses[I2CBus];
}

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//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM.h"
#include <cassert>
Timer::Timer(Timer_Key t) : TIMER_KEY(t){
}
Timer::Timer() : TIMER_KEY(Timer_Key::S_TIM_INVALID){
}
void Timer::start() {
getTimerRegister(TIMER_KEY)->CR1 |= TIM_CR1_CEN;
getTimerRegister(TIMER_KEY)->EGR |= TIM_EGR_UG; //load prescaler reg and ARR
enableInterrupt();
}
void Timer::stop() {
getTimerRegister(TIMER_KEY)->CR1 &= ~TIM_CR1_CEN;
}
void Timer::setPrescaler(uint16_t presc) {
getTimerRegister(TIMER_KEY)->PSC = presc;
}
void Timer::setARR(uint16_t arr) {
getTimerRegister(TIMER_KEY)->ARR = arr;
}
void Timer::enableInterrupt() {
getTimerRegister(TIMER_KEY)->DIER |= TIM_DIER_UIE;
NVIC_EnableIRQ(getIRQn(TIMER_KEY));
}
void Timer::init(uint32_t prescaler, uint32_t autoReload) {
TIM_RCC_Enable rcc = getTimerRCC(TIMER_KEY);
*rcc.busEnableReg |= (1 << rcc.offset);
setPrescaler(prescaler);
setARR(autoReload);
}
Timer &TimerManager::get(Timer_Key timer_key) {
//Ensure that we don't try to get invalid timers
assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
Timer& selected = timers[static_cast<int>(timer_key)];
//Timer queried is not initialized yet (defaults to invalid)
if(selected.TIMER_KEY == Timer_Key::S_TIM_INVALID){
timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
}
return timers[static_cast<int>(timer_key)];
}

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SHAL/Src/STM32L4XX/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp Normal file
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//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM_CALLBACK.h"
DEFINE_TIMER_IRQ(Timer_Key::S_TIM1, TIM1_BRK_UP_TRG_COM_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM2, TIM2_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM3, TIM3_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM14, TIM14_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM15, TIM15_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM16, TIM16_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM17, TIM17_IRQHandler)
void registerTimerCallback(Timer_Key key, TimerCallback callback){
timer_callbacks[static_cast<int>(key)] = callback;
}

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/**
******************************************************************************
* @file SHAL_TIM.h
* @author Luca Lizaranzu
* @brief Related to USART and SHAL_UART abstractions
******************************************************************************
*/
#include "SHAL_UART.h"
#include "SHAL_GPIO.h"
void SHAL_UART::init(const UART_Pair pair){
m_UARTPair = pair;
SHAL_UART_Pair uart_pair = getUARTPair(pair); //Get the UART_PAIR information to be initialized
//Get the SHAL_GPIO pins for this SHAL_UART setup
GPIO_Key Tx_Key = uart_pair.TxKey; //Tx pin
GPIO_Key Rx_Key = uart_pair.RxKey; //Rx pin
GET_GPIO(Tx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
GET_GPIO(Rx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
GET_GPIO(Tx_Key).setAlternateFunction(uart_pair.TxAlternateFunctionMask);
GET_GPIO(Rx_Key).setAlternateFunction(uart_pair.RxAlternateFunctionMask);
SHAL_UART_ENABLE_REG pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the SHAL_UART channel
*pairUARTEnable.reg |= pairUARTEnable.mask; //Enable SHAL_UART line
}
void SHAL_UART::begin(uint32_t baudRate) volatile {
USART_TypeDef* usart = getUARTPair(m_UARTPair).USARTReg;
usart->CR1 &= ~USART_CR1_UE; //Disable USART
usart->CR1 = 0; //Clear USART config
usart->CR1 = USART_CR1_TE | USART_CR1_RE; //Tx enable and Rx Enable
usart->BRR = 8000000 / baudRate; //MAKE SURE ANY FUNCTION THAT CHANGES CLOCK UPDATES THIS! //TODO DO NOT HARDCODE THIS SHIT
usart->CR1 |= USART_CR1_UE;
}
void SHAL_UART::sendString(const char *s) volatile {
while (*s) sendChar(*s++); //Send chars while we haven't reached end of s
}
void SHAL_UART::sendChar(char c) volatile {
USART_TypeDef* usart = getUARTPair(m_UARTPair).USARTReg;
while(!(usart->ISR & USART_ISR_TXE)); //Wait for usart to finish what it's doing
usart->TDR = c; //Send character
}
SHAL_UART& UARTManager::get(uint8_t uart) {
if(uart > NUM_USART_LINES - 1){
assert(false);
//Memory fault
}
return m_UARTs[uart];
}

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/**
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | MSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/** @addtogroup STM32L4xx_System_Private_Includes
* @{
*/
#include "stm32l4xx.h"
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
#if defined(USER_VECT_TAB_ADDRESS)
/* Configure the Vector Table location -------------------------------------*/
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
/* Get MSI Range frequency--------------------------------------------------*/
if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
{ /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange;
break;
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource)
{
case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm);
break;
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr;
break;
default:
SystemCoreClock = msirange;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

0
SHAL/Src/System/syscalls.c → SHAL/Src/Universal/syscalls.c
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0
SHAL/Src/System/sysmem.c → SHAL/Src/Universal/sysmem.c
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