lucalizaranzu/Shmingo-HAL
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Added core tools, added ADC abstractions for different registers

Browse Source
This commit is contained in:
Ea-r-th
2025-10-12 20:53:40 -07:00
parent c76dbee94c
commit cba6c00562
13 changed files with 291 additions and 95 deletions
Download Patch File Download Diff File Expand all files Collapse all files

78
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_L432KC.h
View File

@@ -10,12 +10,84 @@
#define SHAL_ADC1 SHAL_ADC(1)
enum class ADC_Key : uint8_t{
S_ADC1,
NUM_ADC,
INVALID
S_ADC1 = 0,
NUM_ADC = 1,
INVALID = 255
};
enum class ADC_Clock_Source : uint8_t {
SHAL_SYSCLK,
SHAL_PLLSAI1,
SHAL_PLL,
SHAL_MSI
};
static volatile ADC_TypeDef* ADC_TABLE[1] = { //Lookup table for ADCs
ADC1,
};
SHAL_ADC_Common_Control_Reg getADCCommonControl() {
return {&ADC1_COMMON->CCR ,ADC_CCR_VREFEN,ADC_CCR_TSEN,ADC_CCR_VBATEN};
}
SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
SHAL_ADC_RCC_Enable_Reg res = {nullptr, RCC_AHB2ENR_ADCEN};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN, ADC_CR_ADDIS, ADC_CR_ADCAL, ADC_CR_ADSTART};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
return res;
}
SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
SHAL_ADC_Config_Reg res = {nullptr, ADC_CFGR_CONT, ADC_CFGR_RES_Pos, ADC_CFGR_ALIGN_Pos};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CFGR);
return res;
}
SHAL_ADC_ISR getADCISR(ADC_Key key){
SHAL_ADC_ISR res = {nullptr, ADC_ISR_EOC};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
return res;
}
SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
constexpr uint32_t ADCSEL_MASK = RCC_CCIPR_ADCSEL_Msk; // covers bits 29:28
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, ADCSEL_MASK, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
switch(clockSource){
case ADC_Clock_Source::SHAL_PLLSAI1:
res.mask = 1U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_PLL:
res.mask = 2U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_SYSCLK:
res.mask = 3U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_MSI:
break; //TODO implement this
}
return res;
}
constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
switch(key){
case ADC_Key::S_ADC1:

11
SHAL/Include/Peripheral/ADC/SHAL_ADC.h
View File

@@ -20,18 +20,22 @@ public:
SHAL_Result calibrate();
SHAL_Result configureResolution(SHAL_ADC_Resolution resolution);
SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment);
/// Performs analog to digital conversion on a single channel, one time
/// \param channel Channel to be converted
/// \param time ADC_SampleTime - amount of clock cycles per conversion
/// \return resulting value
uint16_t singleConvertSingle(ADC_Channel channel, ADC_SampleTime time = ADC_SampleTime::C239);
uint16_t singleConvertSingle(SHAL_ADC_Channel channel, ADC_SampleTime time = ADC_SampleTime::C239);
/// Performs analog to digital conversion on multiple channels, one time
/// \param channels Pointer to an array of channels to convert
/// \param numChannels Number of channels to convert
/// \param result Pointer to store converted channel results in
/// \param time ADC_SampleTime - amount of clock cycles per conversion
void multiConvertSingle(ADC_Channel* channels, const int numChannels, uint16_t* result, ADC_SampleTime time = ADC_SampleTime::C239);
void multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, ADC_SampleTime time = ADC_SampleTime::C239);
@@ -41,6 +45,9 @@ private:
ADC_Key m_ADCKey = ADC_Key::INVALID;
bool isValid();
SHAL_Result disable();
};

101
SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
View File

@@ -5,26 +5,75 @@
#ifndef SHMINGO_HAL_SHAL_ADC_TYPES_H
#define SHMINGO_HAL_SHAL_ADC_TYPES_H
enum class ADC_Channel : uint32_t {
CH0 = ADC_CHSELR_CHSEL0,
CH1 = ADC_CHSELR_CHSEL1,
CH2 = ADC_CHSELR_CHSEL2,
CH3 = ADC_CHSELR_CHSEL3,
CH4 = ADC_CHSELR_CHSEL4,
CH5 = ADC_CHSELR_CHSEL5,
CH6 = ADC_CHSELR_CHSEL6,
CH7 = ADC_CHSELR_CHSEL7,
CH8 = ADC_CHSELR_CHSEL8,
CH9 = ADC_CHSELR_CHSEL9,
CH10 = ADC_CHSELR_CHSEL10,
CH11 = ADC_CHSELR_CHSEL11,
CH12 = ADC_CHSELR_CHSEL12,
CH13 = ADC_CHSELR_CHSEL13,
CH14 = ADC_CHSELR_CHSEL14,
CH15 = ADC_CHSELR_CHSEL15,
CHTemp = ADC_CHSELR_CHSEL16,
CHRef = ADC_CHSELR_CHSEL17,
CHBat = ADC_CHSELR_CHSEL18
struct SHAL_ADC_Common_Control_Reg {
volatile uint32_t* reg;
uint32_t VoltageRefEnable;
uint32_t TempSensorEnable;
uint32_t VBatteryEnable;
};
struct SHAL_ADC_RCC_Enable_Reg {
volatile uint32_t* reg;
uint32_t mask;
};
struct SHAL_ADC_Control_Reg {
volatile uint32_t* reg;
uint32_t enable_mask;
uint32_t disable_mask;
uint32_t calibration_mask;
uint32_t start_mask;
};
struct SHAL_ADC_Config_Reg {
volatile uint32_t* reg;
uint32_t continue_mask;
uint32_t resolution_offset;
uint32_t alignment_offset;
};
struct SHAL_ADC_Data_Reg {
volatile uint32_t* reg;
uint32_t mask;
};
struct SHAL_ADC_ISR {
volatile uint32_t* reg;
uint32_t end_of_conversion_mask;
};
struct SHAL_ADC_Clock_Reg {
volatile uint32_t* reg;
uint32_t clear;
uint32_t mask;
};
enum class SHAL_ADC_Channel : uint32_t {
CH0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
CH8,
CH9,
CH10,
CH11,
CH12,
CH13,
CH14,
CH15,
CHTemp,
CHRef,
CHBat
};
enum class ADC_SampleTime : uint32_t {
@@ -38,4 +87,16 @@ enum class ADC_SampleTime : uint32_t {
C239 = 0x07 //239.5 cycles
};
enum class SHAL_ADC_Resolution : uint8_t {
B12 = 0x00,
B10 = 0x01,
B8 = 0x02,
B6 = 0x03,
};
enum class SHAL_ADC_Alignment : uint8_t {
RIGHT = 0x00,
LEFT = 0x01,
};
#endif //SHMINGO_HAL_SHAL_ADC_TYPES_H