From d763965cb875b7c6ffbd9462cda4161fecf10ccf Mon Sep 17 00:00:00 2001
From: Luca <luca.lizaranzu@gmail.com>
Date: Sat, 6 Sep 2025 19:49:36 -0700
Subject: [PATCH] Created structs and enums for alternate function UART pins

---
 SHAL/Include/Core/SHAL_CORE.h                 |  6 +--
 .../Peripheral/GPIO/Reg/SHAL_GPIO_REG.h       | 39 +++++++++++++++++++
 .../GPIO/Reg/SHAL_GPIO_REG_F072xB.h           | 38 +++++++++++++++++-
 SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h      |  2 +-
 SHAL/Src/Peripheral/GPIO/SHAL_GPIO.cpp        |  2 +-
 SHAL/Src/main.cpp                             |  4 +-
 6 files changed, 81 insertions(+), 10 deletions(-)
 create mode 100644 SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h

diff --git a/SHAL/Include/Core/SHAL_CORE.h b/SHAL/Include/Core/SHAL_CORE.h
index 5b3f5c2..8b42e57 100644
--- a/SHAL/Include/Core/SHAL_CORE.h
+++ b/SHAL/Include/Core/SHAL_CORE.h
@@ -23,11 +23,7 @@ struct SHAL_Peripheral_Register {
     unsigned long offset;
 };
 
-struct SHAL_EXTIO_Register{
-    volatile uint32_t* EXT_ICR;
-    unsigned long mask;
-    IRQn_Type IRQN;
-};
+
 
 //---------------------------------------------------------
 
diff --git a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h
new file mode 100644
index 0000000..144000f
--- /dev/null
+++ b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h
@@ -0,0 +1,39 @@
+//
+// Created by Luca on 9/6/2025.
+//
+
+#ifndef SHMINGO_HAL_SHAL_GPIO_REG_H
+#define SHMINGO_HAL_SHAL_GPIO_REG_H
+
+#include "SHAL_CORE.h"
+
+struct SHAL_EXTIO_Register{
+    volatile uint32_t* EXT_ICR;
+    uint32_t mask;
+    IRQn_Type IRQN;
+};
+
+enum class AF_Mask : uint8_t{
+    AF0 = 0x00,
+    AF1 = 0x01,
+    AF2 = 0x02,
+    AF3 = 0x03,
+    AF4 = 0x04,
+    AF5 = 0x05,
+    AF6 = 0x06,
+    AF7 = 0x07
+};
+
+//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping
+struct SHAL_UART_Pair{
+    uint8_t TxPinNumber;
+    uint8_t RxPinNumber;
+    volatile uint32_t* TxReg;
+    volatile uint32_t* RxReg;
+    AF_Mask TxMask;
+    AF_Mask RxMask;
+};
+
+
+
+#endif //SHMINGO_HAL_SHAL_GPIO_REG_H
diff --git a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h
index f2e7d31..7e4b43f 100644
--- a/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h
+++ b/SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h
@@ -8,7 +8,7 @@
 #include <stm32f072xb.h>
 #include <cassert>
 
-#include "SHAL_CORE.h"
+#include "SHAL_GPIO_REG.h"
 
 #define AVAILABLE_PORTS 3
 #define PINS_PER_PORT 16
@@ -29,6 +29,40 @@ enum class GPIO_Key : uint8_t {
     INVALID
 };
 
+//Valid usart Tx and Rx pairings for STM32F072
+enum class UART_Pair : uint8_t{
+    //UART1
+    Tx1A9_Rx1A10,
+    Tx1B6_Rx1B7,
+
+    //UART2
+    Tx2A2_Rx2A3,
+    Tx2A14_Rx2A15,
+
+    //UART3
+    Tx3B10_Rx3B11,
+    Tx3C4_Rx3C5,
+    Tx3C10_Rx3C11,
+
+    //UART4
+    Tx4A0_Rx4A1,
+    Tx4C10_Rx4C11
+};
+
+constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){
+    switch(pair){
+        case UART_Pair::Tx1A9_Rx1A10: return {9,10,&GPIOA->AFR[1],&GPIOA->AFR[1],AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx1B6_Rx1B7: return {6,7,&GPIOB->AFR[0],&GPIOB->AFR[0],AF_Mask::AF0,AF_Mask::AF0};
+        case UART_Pair::Tx2A2_Rx2A3: return {2,3,&GPIOA->AFR[0],&GPIOA->AFR[0],AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx2A14_Rx2A15: return {14,15,&GPIOA->AFR[1],&GPIOA->AFR[1],AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx3B10_Rx3B11: return {10,11,&GPIOB->AFR[1],&GPIOB->AFR[1],AF_Mask::AF4,AF_Mask::AF4};
+        case UART_Pair::Tx3C4_Rx3C5: return {4,5,&GPIOC->AFR[0],&GPIOC->AFR[0],AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx3C10_Rx3C11: return {10,11,&GPIOC->AFR[1],&GPIOC->AFR[1],AF_Mask::AF1,AF_Mask::AF1};
+        case UART_Pair::Tx4A0_Rx4A1: return {0,1,&GPIOA->AFR[0],&GPIOA->AFR[0],AF_Mask::AF4,AF_Mask::AF4};
+        case UART_Pair::Tx4C10_Rx4C11: return {10,11,&GPIOC->AFR[1],&GPIOC->AFR[1],AF_Mask::AF0,AF_Mask::AF0};
+    }
+}
+
 
 constexpr SHAL_Peripheral getGPIORegister(const GPIO_Key g){
     switch(g) {
@@ -269,4 +303,6 @@ constexpr unsigned int getGPIOPortNumber(const GPIO_Key g){
     __builtin_unreachable();
 }
 
+
+
 #endif //SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H
diff --git a/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h b/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
index 44f4ed8..2d32af9 100644
--- a/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
+++ b/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
@@ -40,7 +40,7 @@ class GPIO{
 
 public:
 
-    void toggle();
+    void toggle() volatile;
 
     //TODO replace stupid offset hack from APB
     void setHigh();
diff --git a/SHAL/Src/Peripheral/GPIO/SHAL_GPIO.cpp b/SHAL/Src/Peripheral/GPIO/SHAL_GPIO.cpp
index 34db28f..ce2edfb 100644
--- a/SHAL/Src/Peripheral/GPIO/SHAL_GPIO.cpp
+++ b/SHAL/Src/Peripheral/GPIO/SHAL_GPIO.cpp
@@ -55,7 +55,7 @@ void GPIO::setHigh() {
     static_cast<GPIO_TypeDef*>(gpioPeripheral.registers)->ODR |= (1 << gpioPeripheral.global_offset);
 }
 
-void GPIO::toggle() {
+void GPIO::toggle() volatile {
     auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
     static_cast<GPIO_TypeDef*>(gpioPeripheral.registers)->ODR ^= (1 << gpioPeripheral.global_offset);
 }
diff --git a/SHAL/Src/main.cpp b/SHAL/Src/main.cpp
index ab8318c..773b294 100644
--- a/SHAL/Src/main.cpp
+++ b/SHAL/Src/main.cpp
@@ -2,8 +2,8 @@
 #include "stm32f0xx.h"
 
 
-GPIO* blueLED = nullptr;
-GPIO* greenLED = nullptr;
+volatile GPIO* blueLED = nullptr;
+volatile GPIO* greenLED = nullptr;
 
 extern "C" void EXTI0_1_IRQHandler(void) {
     if (EXTI->PR & (1 << 0)) {   //Check pending flag