Bare functionality finished for basic GPIO pin abstraction

CMakeLists.txt

@@ -29,14 +29,17 @@ set(MX_INCLUDE_DIRECTORIES
 
 set(PROJECT_INCLUDE_DIRECTORIES
     ${CMAKE_CURRENT_SOURCE_DIR}
-    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include/Timer
-    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include/Timer/Reg
-    ${CMAKE_CURRENT_SOURCE_DIR}/Core/Include
+        SHAL/Include/Core/
+        SHAL/Include/Peripheral/Timer
+        SHAL/Include/Peripheral/Timer/Reg
+        SHAL/Include/Peripheral/GPIO
+        SHAL/Include/Peripheral/GPIO/Reg
+        ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include
 )
 
 file(GLOB_RECURSE PROJECT_SOURCES
-    ${CMAKE_CURRENT_SOURCE_DIR}/Core/*.c
-    ${CMAKE_CURRENT_SOURCE_DIR}/Core/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/*.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/*.cpp
 )
 
 add_executable(${EXECUTABLE}

Core/Src/main.cpp

@@ -1,51 +0,0 @@
-#include "SHAL.h"
-#include "stm32f0xx.h"
-
-extern "C" void EXTI0_1_IRQHandler(void) {
-    if (EXTI->PR & (1 << 0)) {   //Check pending flag
-        EXTI->PR |= (1 << 0);    //Clear it by writing 1
-        GPIOA->ODR ^= (1 << 5);
-    }
-}
-
-void tim2Handler(){
-    GPIOA->ODR ^= (1 << 4);
-}
-
-int main() {
-    RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
-    RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
-
-    Timer timer2 = getTimer(Timer_Key::S_TIM2);
-
-    timer2.setPrescaler(8000 - 1);
-    timer2.setARR(500 - 1);
-    timer2.setCallbackFunc(tim2Handler);
-    timer2.start();
-
-
-    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; //Enable SYSCFG clock (needed for EXTI)
-
-    GPIOA->MODER &= ~(0b11 << (4 * 2));
-    GPIOA->MODER |= (0b1 << (4 * 2));
-
-    GPIOA->MODER &= ~(0x3 << (5 * 2));
-    GPIOA->MODER |=  (0x1 << (5 * 2));
-
-    GPIOB->MODER &= ~(0x3 << (0 * 2));
-    GPIOB->MODER |=  (0x0 << (0 * 2));
-
-    SYSCFG->EXTICR[0] &= ~SYSCFG_EXTICR1_EXTI0; // Clear EXTI0 mapping
-    SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PB; // Map PA0 -> EXTI0
-
-    EXTI->IMR |= (1 << 0);   // Unmask EXTI0
-    EXTI->RTSR |= (1 << 0);  // Trigger on rising edge
-
-    NVIC_EnableIRQ(EXTI0_1_IRQn); // EXTI lines 0 and 1 share an IRQ vector
-
-    __enable_irq();
-
-    while (true) {
-    	__WFI();
-    }
-}

Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h

@@ -467,7 +467,7 @@ typedef struct
   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup TIMER_KEY register,                                 Address offset: 0x14 */
        uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x18 */
   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
        uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x20 */

Drivers/CMSIS/Include/cmsis_armcc.h

@@ -101,7 +101,7 @@
   #define __RESTRICT                             __restrict
 #endif
 
-/* ###########################  Core Function Access  ########################### */
+/* ###########################  SHAL Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
@@ -374,7 +374,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-/* ##########################  Core Instruction Access  ######################### */
+/* ##########################  SHAL Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
   @{

Drivers/CMSIS/Include/cmsis_armclang.h

@@ -112,7 +112,7 @@
 #endif
 
 
-/* ###########################  Core Function Access  ########################### */
+/* ###########################  SHAL Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
@@ -770,7 +770,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-/* ##########################  Core Instruction Access  ######################### */
+/* ##########################  SHAL Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
   @{

Drivers/CMSIS/Include/cmsis_gcc.h

@@ -115,7 +115,7 @@
 #endif
 
 
-/* ###########################  Core Function Access  ########################### */
+/* ###########################  SHAL Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
@@ -810,7 +810,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 /*@} end of CMSIS_Core_RegAccFunctions */
 
 
-/* ##########################  Core Instruction Access  ######################### */
+/* ##########################  SHAL Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
   @{

Drivers/CMSIS/Include/core_armv8mbl.h

@@ -1033,7 +1033,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -1109,7 +1109,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
   #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
   #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
   #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
@@ -1138,7 +1138,7 @@ typedef struct
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
   #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< SHAL Debug Base Address           (non-secure address space) */
   #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
   #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
   #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
@@ -1146,7 +1146,7 @@ typedef struct
   #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
   #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
   #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct   (non-secure address space) */
 
   #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
     #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */

Drivers/CMSIS/Include/core_armv8mml.h

@@ -1863,7 +1863,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -1969,7 +1969,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
   #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
   #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
   #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
@@ -2003,7 +2003,7 @@ typedef struct
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
   #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< SHAL Debug Base Address           (non-secure address space) */
   #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
   #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
   #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
@@ -2012,7 +2012,7 @@ typedef struct
   #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
   #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
   #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct   (non-secure address space) */
 
   #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
     #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */

Drivers/CMSIS/Include/core_cm0.h

@@ -530,7 +530,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

Drivers/CMSIS/Include/core_cm0plus.h

@@ -644,7 +644,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

Drivers/CMSIS/Include/core_cm1.h

@@ -556,7 +556,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

Drivers/CMSIS/Include/core_cm23.h

@@ -1108,7 +1108,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -1184,7 +1184,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
   #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
   #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
   #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
@@ -1213,7 +1213,7 @@ typedef struct
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
   #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< SHAL Debug Base Address           (non-secure address space) */
   #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
   #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
   #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
@@ -1221,7 +1221,7 @@ typedef struct
   #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
   #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
   #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct   (non-secure address space) */
 
   #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
     #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */

Drivers/CMSIS/Include/core_cm3.h

@@ -1296,7 +1296,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -1379,7 +1379,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

Drivers/CMSIS/Include/core_cm33.h

@@ -1938,7 +1938,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -2044,7 +2044,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
   #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
   #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
   #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
@@ -2078,7 +2078,7 @@ typedef struct
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
   #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< SHAL Debug Base Address           (non-secure address space) */
   #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
   #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
   #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
@@ -2087,7 +2087,7 @@ typedef struct
   #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
   #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
   #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< SHAL Debug configuration struct   (non-secure address space) */
 
   #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
     #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */

Drivers/CMSIS/Include/core_cm4.h

@@ -1467,7 +1467,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -1550,7 +1550,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

Drivers/CMSIS/Include/core_cm7.h

@@ -1675,7 +1675,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -1758,7 +1758,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

Drivers/CMSIS/Include/core_sc000.h

@@ -653,7 +653,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

Drivers/CMSIS/Include/core_sc300.h

@@ -1276,7 +1276,7 @@ typedef struct
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register Definitions */
+/* Debug SHAL Register Selector Register Definitions */
 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
@@ -1359,7 +1359,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SHAL Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

SHAL/Include/Core/SHAL_CORE.h

@@ -0,0 +1,68 @@
+/**
+  ******************************************************************************
+  * @file    SHAL_CORE.h
+  * @author  Luca Lizaranzu
+  * @brief   Defines universal macros and objects used across all STM32 families
+  * Includes for ST Microelectronics pre-made C headers for STM32 device families
+  ******************************************************************************
+  */
+#ifndef SHMINGO_HAL_SHAL_CORE_H
+#define SHMINGO_HAL_SHAL_CORE_H
+
+#include <cstdint>
+
+//Universal structs and defines ---------------------------
+
+struct SHAL_Peripheral {
+    void* registers;
+    unsigned long global_offset;
+};
+
+struct SHAL_Peripheral_Register {
+    volatile uint32_t* reg;
+    unsigned long offset;
+};
+
+
+//---------------------------------------------------------
+
+
+#if defined(STM32F030x6)
+#include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+#include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+#include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+#include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+#include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+#include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+#include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+#include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+#include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+#include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+#include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+#include "stm32f072xb.h"
+#include "SHAL_TIM_REG_F072xB.h"
+#elif defined(STM32F078xx)
+#include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+  #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+  #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+  #include "stm32f030xc.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+
+#endif //SHMINGO_HAL_SHAL_CORE_H

SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h

@@ -0,0 +1,212 @@
+//
+// Created by Luca on 8/29/2025.
+//
+
+#ifndef SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H
+#define SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H
+
+#include <stm32f072xb.h>
+#include <cassert>
+
+#include "SHAL_CORE.h"
+
+#define AVAILABLE_PORTS 3
+#define PINS_PER_PORT 16
+
+#define AVAILABLE_GPIO \
+    X(A0) X(A1) X(A2) X(A3) X(A4) X(A5) X(A6) X(A7) X(A8) X(A9) X(A10) X(A11) X(A12) X(A13) X(A14) X(A15) \
+    X(B0) X(B1) X(B2) X(B3) X(B4) X(B5) X(B6) X(B7) X(B8) X(B9) X(B10) X(B11) X(B12) X(B13) X(B14) X(B15) \
+    X(C0) X(C1) X(C2) X(C3) X(C4) X(C5) X(C6) X(C7) X(C8) X(C9) X(C10) X(C11) X(C12) X(C13) X(C14) X(C15)
+
+
+//Build enum map of available GPIO pins
+enum class GPIO_Key : uint8_t {
+    #define X(key) key,
+        AVAILABLE_GPIO
+    #undef X
+    NUM_GPIO,
+    INVALID
+};
+
+
+constexpr SHAL_Peripheral getGPIORegister(const GPIO_Key g){
+    switch(g) {
+        case GPIO_Key::A0: return {GPIOA,0};
+        case GPIO_Key::A1: return {GPIOA,1};
+        case GPIO_Key::A2: return {GPIOA,2};
+        case GPIO_Key::A3: return {GPIOA,3};
+        case GPIO_Key::A4: return {GPIOA,4};
+        case GPIO_Key::A5: return {GPIOA,5};
+        case GPIO_Key::A6: return {GPIOA,6};
+        case GPIO_Key::A7: return {GPIOA,7};
+        case GPIO_Key::A8: return {GPIOA,8};
+        case GPIO_Key::A9: return {GPIOA,9};
+        case GPIO_Key::A10: return {GPIOA,10};
+        case GPIO_Key::A11: return {GPIOA,11};
+        case GPIO_Key::A12: return {GPIOA,12};
+        case GPIO_Key::A13: return {GPIOA,13};
+        case GPIO_Key::A14: return {GPIOA,14};
+        case GPIO_Key::A15: return {GPIOA,15};
+        case GPIO_Key::B0: return {GPIOB,0};
+        case GPIO_Key::B1: return {GPIOB,1};
+        case GPIO_Key::B2: return {GPIOB,2};
+        case GPIO_Key::B3: return {GPIOB,3};
+        case GPIO_Key::B4: return {GPIOB,4};
+        case GPIO_Key::B5: return {GPIOB,5};
+        case GPIO_Key::B6: return {GPIOB,6};
+        case GPIO_Key::B7: return {GPIOB,7};
+        case GPIO_Key::B8: return {GPIOB,8};
+        case GPIO_Key::B9: return {GPIOB,9};
+        case GPIO_Key::B10: return {GPIOB,10};
+        case GPIO_Key::B11: return {GPIOB,11};
+        case GPIO_Key::B12: return {GPIOB,12};
+        case GPIO_Key::B13: return {GPIOB,13};
+        case GPIO_Key::B14: return {GPIOB,14};
+        case GPIO_Key::B15: return {GPIOB,15};
+        case GPIO_Key::C0: return {GPIOC,0};
+        case GPIO_Key::C1: return {GPIOC,1};
+        case GPIO_Key::C2: return {GPIOC,2};
+        case GPIO_Key::C3: return {GPIOC,3};
+        case GPIO_Key::C4: return {GPIOC,4};
+        case GPIO_Key::C5: return {GPIOC,5};
+        case GPIO_Key::C6: return {GPIOC,6};
+        case GPIO_Key::C7: return {GPIOC,7};
+        case GPIO_Key::C8: return {GPIOC,8};
+        case GPIO_Key::C9: return {GPIOC,9};
+        case GPIO_Key::C10: return {GPIOC,10};
+        case GPIO_Key::C11: return {GPIOC,11};
+        case GPIO_Key::C12: return {GPIOC,12};
+        case GPIO_Key::C13: return {GPIOC,13};
+        case GPIO_Key::C14: return {GPIOC,14};
+        case GPIO_Key::C15: return {GPIOC,15};
+        case GPIO_Key::INVALID:
+        case GPIO_Key::NUM_GPIO:
+            assert(false);
+            return SHAL_Peripheral(nullptr,0); //Unreachable
+    }
+    __builtin_unreachable();
+}
+
+constexpr SHAL_Peripheral_Register getGPIORCCEnable(const GPIO_Key g){
+    switch(g) {
+        case GPIO_Key::A0:
+        case GPIO_Key::A1:
+        case GPIO_Key::A2:
+        case GPIO_Key::A3:
+        case GPIO_Key::A4:
+        case GPIO_Key::A5:
+        case GPIO_Key::A6:
+        case GPIO_Key::A7:
+        case GPIO_Key::A8:
+        case GPIO_Key::A9:
+        case GPIO_Key::A10:
+        case GPIO_Key::A11:
+        case GPIO_Key::A12:
+        case GPIO_Key::A13:
+        case GPIO_Key::A14:
+        case GPIO_Key::A15:
+            return {&RCC->AHBENR, RCC_AHBENR_GPIOAEN_Pos};
+        case GPIO_Key::B0:
+        case GPIO_Key::B1:
+        case GPIO_Key::B2:
+        case GPIO_Key::B3:
+        case GPIO_Key::B4:
+        case GPIO_Key::B5:
+        case GPIO_Key::B6:
+        case GPIO_Key::B7:
+        case GPIO_Key::B8:
+        case GPIO_Key::B9:
+        case GPIO_Key::B10:
+        case GPIO_Key::B11:
+        case GPIO_Key::B12:
+        case GPIO_Key::B13:
+        case GPIO_Key::B14:
+        case GPIO_Key::B15:
+            return {&RCC->AHBENR, RCC_AHBENR_GPIOBEN_Pos};
+        case GPIO_Key::C0:
+        case GPIO_Key::C1:
+        case GPIO_Key::C2:
+        case GPIO_Key::C3:
+        case GPIO_Key::C4:
+        case GPIO_Key::C5:
+        case GPIO_Key::C6:
+        case GPIO_Key::C7:
+        case GPIO_Key::C8:
+        case GPIO_Key::C9:
+        case GPIO_Key::C10:
+        case GPIO_Key::C11:
+        case GPIO_Key::C12:
+        case GPIO_Key::C13:
+        case GPIO_Key::C14:
+        case GPIO_Key::C15:
+            return {&RCC->AHBENR, RCC_AHBENR_GPIOCEN_Pos};
+        case GPIO_Key::INVALID:
+        case GPIO_Key::NUM_GPIO:
+            assert(false);
+            return SHAL_Peripheral_Register(nullptr,0); //Unreachable
+    }
+    __builtin_unreachable();
+}
+
+constexpr unsigned int getGPIOPortNumber(const GPIO_Key g){
+    switch(g) {
+        case GPIO_Key::A0:
+        case GPIO_Key::A1:
+        case GPIO_Key::A2:
+        case GPIO_Key::A3:
+        case GPIO_Key::A4:
+        case GPIO_Key::A5:
+        case GPIO_Key::A6:
+        case GPIO_Key::A7:
+        case GPIO_Key::A8:
+        case GPIO_Key::A9:
+        case GPIO_Key::A10:
+        case GPIO_Key::A11:
+        case GPIO_Key::A12:
+        case GPIO_Key::A13:
+        case GPIO_Key::A14:
+        case GPIO_Key::A15:
+            return 0;
+        case GPIO_Key::B0:
+        case GPIO_Key::B1:
+        case GPIO_Key::B2:
+        case GPIO_Key::B3:
+        case GPIO_Key::B4:
+        case GPIO_Key::B5:
+        case GPIO_Key::B6:
+        case GPIO_Key::B7:
+        case GPIO_Key::B8:
+        case GPIO_Key::B9:
+        case GPIO_Key::B10:
+        case GPIO_Key::B11:
+        case GPIO_Key::B12:
+        case GPIO_Key::B13:
+        case GPIO_Key::B14:
+        case GPIO_Key::B15:
+            return 1;
+        case GPIO_Key::C0:
+        case GPIO_Key::C1:
+        case GPIO_Key::C2:
+        case GPIO_Key::C3:
+        case GPIO_Key::C4:
+        case GPIO_Key::C5:
+        case GPIO_Key::C6:
+        case GPIO_Key::C7:
+        case GPIO_Key::C8:
+        case GPIO_Key::C9:
+        case GPIO_Key::C10:
+        case GPIO_Key::C11:
+        case GPIO_Key::C12:
+        case GPIO_Key::C13:
+        case GPIO_Key::C14:
+        case GPIO_Key::C15:
+            return 2;
+        case GPIO_Key::INVALID:
+        case GPIO_Key::NUM_GPIO:
+            assert(false);
+            return 0;
+    }
+    __builtin_unreachable();
+}
+
+#endif //SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H

SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h

@@ -0,0 +1,62 @@
+//
+// Created by Luca on 8/29/2025.
+//
+
+#ifndef SHMINGO_HAL_SHAL_GPIO_H
+#define SHMINGO_HAL_SHAL_GPIO_H
+
+#include "SHAL_CORE.h"
+
+#include <cassert>
+#include "SHAL_GPIO_REG_F072xB.h"
+
+enum class PinMode : uint8_t{
+    INPUT_MODE,
+    OUTPUT_MODE,
+    ALTERNATE_FUNCTION_MODE,
+    ANALOG_MODE,
+    INVALID
+};
+
+unsigned long getPinMode(PinMode mode);
+
+//Abstraction of GPIO registers
+class GPIO{
+
+public:
+
+    void toggle();
+
+    //TODO replace stupid offset hack from APB
+    void setHigh();
+    void setLow();
+
+private:
+
+    friend class GPIOManager;
+
+    explicit GPIO(GPIO_Key key, PinMode pinMode);
+    GPIO();
+
+    GPIO_Key m_GPIO_KEY = GPIO_Key::INVALID;
+
+};
+
+
+#define initGPIO(GPIO_KEY, PIN_MODE) GPIOManager::get(GPIO_KEY, PIN_MODE)
+
+//Manages instances of GPIO objects
+class GPIOManager{
+
+public:
+
+    static GPIO& get(GPIO_Key, PinMode pinMode);
+    GPIOManager() = delete;
+
+private:
+
+inline static GPIO m_gpios[AVAILABLE_PORTS][PINS_PER_PORT] = {{}};
+
+};
+
+#endif //SHMINGO_HAL_SHAL_GPIO_H

SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_F072xB.h

@@ -1,28 +1,25 @@
+/**
+  ******************************************************************************
+  * @file    SHAL_TIM_REG.h
+  * @author  Luca Lizaranzu
+  * @brief   Defines universal macros and objects used across all STM32 families
+  ******************************************************************************
+  */
+
 #ifndef SHAL_TIM_REG_H
 #define SHAL_TIM_REG_H
 
-#include <cstdint>
 #include <cassert>
 #include <stm32f072xb.h>
 
+#include "SHAL_CORE.h"
 
-enum class Bus {
-    AHB,
-    APB1,
-    APB2,
-    INVALID
-};
-
-struct RCC_Peripheral {
-    Bus bus;
-    volatile uint32_t* reg;
-    uint32_t bitmask;
-};
-
-enum class Timer_Key { //For STM32F072
+enum class Timer_Key : uint8_t { //For STM32F072
     S_TIM1,
     S_TIM2,
     S_TIM3,
+    S_TIM6,
+    S_TIM7,
     S_TIM14,
     S_TIM15,
     S_TIM16,
@@ -32,20 +29,22 @@ enum class Timer_Key { //For STM32F072
 };
 
 
-//Get timer peripheral struct including bus register, enable mask, timer mask
-constexpr RCC_Peripheral getTimerRCC(Timer_Key t) {
+//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
+constexpr SHAL_Peripheral_Register getTimerRCC(Timer_Key t) {
     switch(t) {
-        case Timer_Key::S_TIM1:  return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
-        case Timer_Key::S_TIM2:  return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM2EN};
-        case Timer_Key::S_TIM3:  return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM3EN};
-        case Timer_Key::S_TIM14: return {Bus::APB1, &RCC->APB1ENR, RCC_APB1ENR_TIM14EN};
-        case Timer_Key::S_TIM15: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
-        case Timer_Key::S_TIM16: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
-        case Timer_Key::S_TIM17: return {Bus::APB2, &RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
+        case Timer_Key::S_TIM1:  return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_Pos};
+        case Timer_Key::S_TIM2:  return {&RCC->APB1ENR, RCC_APB1ENR_TIM2EN_Pos};
+        case Timer_Key::S_TIM3:  return {&RCC->APB1ENR, RCC_APB1ENR_TIM3EN_Pos};
+        case Timer_Key::S_TIM6:  return {&RCC->APB1ENR, RCC_APB1ENR_TIM6EN_Pos};
+        case Timer_Key::S_TIM7:  return {&RCC->APB1ENR, RCC_APB1ENR_TIM7EN_Pos};
+        case Timer_Key::S_TIM14: return {&RCC->APB1ENR, RCC_APB1ENR_TIM14EN_Pos};
+        case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN_Pos};
+        case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN_Pos};
+        case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN_Pos};
         case Timer_Key::NUM_TIMERS:
         case Timer_Key::S_TIM_INVALID:
             assert(false);
-            return {Bus::INVALID, nullptr, 0};; //Unreachable
+            return {nullptr, 0};; //Unreachable
     }
 
     __builtin_unreachable();
@@ -57,6 +56,8 @@ constexpr volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
         case Timer_Key::S_TIM1:  return TIM1;
         case Timer_Key::S_TIM2:  return TIM2;
         case Timer_Key::S_TIM3:  return TIM3;
+        case Timer_Key::S_TIM6:  return TIM6;
+        case Timer_Key::S_TIM7:  return TIM7;
         case Timer_Key::S_TIM14:  return TIM14;
         case Timer_Key::S_TIM15:  return TIM15;
         case Timer_Key::S_TIM16:  return TIM16;
@@ -74,6 +75,8 @@ constexpr IRQn_Type getIRQn(Timer_Key t) {
         case Timer_Key::S_TIM1:  return TIM1_BRK_UP_TRG_COM_IRQn;
         case Timer_Key::S_TIM2:  return TIM2_IRQn;
         case Timer_Key::S_TIM3:  return TIM3_IRQn;
+        case Timer_Key::S_TIM6:  return TIM6_DAC_IRQn;
+        case Timer_Key::S_TIM7:  return TIM7_IRQn;
         case Timer_Key::S_TIM14: return TIM14_IRQn;
         case Timer_Key::S_TIM15: return TIM15_IRQn;
         case Timer_Key::S_TIM16: return TIM16_IRQn;

SHAL/Include/Peripheral/Timer/SHAL_TIM.h

@@ -1,7 +1,15 @@
+/**
+  ******************************************************************************
+  * @file    SHAL_TIM.h
+  * @author  Luca Lizaranzu
+  * @brief   Declarations of TIMER_KEY related objects
+  ******************************************************************************
+  */
+
 #ifndef SHAL_TIM_H
 #define SHAL_TIM_H
 
-#include "SHAL_TIM_REG.h"
+#include "SHAL_TIM_REG_F072xB.h"
 #include "SHAL_TIM_CALLBACK.h"
 
 #include <array>
@@ -25,9 +33,9 @@ public:
     //Enable interrupts
     void enableInterrupt();
 
-    //Set timer IRQ callback function
+    //Set TIMER_KEY IRQ callback function
     void setCallbackFunc(TimerCallback callback){
-        registerTimerCallback(timer, callback);
+        registerTimerCallback(TIMER_KEY, callback);
     }
 
 private:
@@ -35,12 +43,12 @@ private:
     explicit Timer(Timer_Key t);
     Timer();
 
-    Timer_Key timer;
-    volatile TIM_TypeDef* timer_reg;
+    Timer_Key TIMER_KEY;
 
 };
 
-#define getTimer(timer_key) TimerManager::get(timer_key);
+
+#define getTimer(timer_key) TimerManager::get(timer_key)
 
 //Manages all timers so user does not have to personally initialize
 class TimerManager{

SHAL/Include/Peripheral/Timer/SHAL_TIM_CALLBACK.h

@@ -1,11 +1,16 @@
-//
-// Created by Luca on 8/28/2025.
-//
+/**
+  ******************************************************************************
+  * @file    SHAL.h
+  * @author  Luca Lizaranzu
+  * @brief   Utilities for creating and populating the TIMER_KEY IRQ callback table
+  * globally, see usage in SHAL_TIM.h. Created in use for singleton TIMER_KEY abstractions
+  ******************************************************************************
+  */
 
 #ifndef SHMINGO_HAL_SHAL_TIM_CALLBACK_H
 #define SHMINGO_HAL_SHAL_TIM_CALLBACK_H
 
-#include "SHAL_TIM_REG.h"
+#include "SHAL/Include/Core/SHAL_CORE.h"
 
 #define DEFINE_TIMER_IRQ(key, irq_handler)                \
 extern "C" void irq_handler(void) {                       \

SHAL/Include/SHAL.h

@@ -8,7 +8,7 @@
 #ifndef SHAL_H
 #define SHAL_H
 
-#include "Core/Include/Timer/SHAL_TIM.h"
-
+#include "SHAL_TIM.h"
+#include "SHAL_GPIO.h"
 
 #endif

SHAL/Src/Peripheral/GPIO/SHAL_GPIO.cpp

@@ -0,0 +1,75 @@
+//
+// Created by Luca on 8/30/2025.
+//
+
+#include "SHAL_GPIO.h"
+
+
+unsigned long getPinMode(PinMode mode){
+    switch(mode){
+        case PinMode::INPUT_MODE:
+            return 0b00;
+        case PinMode::OUTPUT_MODE:
+            return 0b01;
+        case PinMode::ALTERNATE_FUNCTION_MODE:
+            return 0b10;
+        case PinMode::ANALOG_MODE:
+            return 0b11;
+        case PinMode::INVALID:
+            assert(false);
+            return 0;
+    }
+    __builtin_unreachable();
+}
+
+
+
+
+GPIO::GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
+    //Do not initialize anything
+}
+
+GPIO::GPIO(GPIO_Key key, PinMode pinMode) : m_GPIO_KEY(key) {
+
+    SHAL_Peripheral gpioPeripheral = getGPIORegister(key);
+
+    auto gpioRegister = static_cast<GPIO_TypeDef*>(gpioPeripheral.registers);
+    unsigned long registerOffset = gpioPeripheral.global_offset;
+
+    volatile unsigned long* gpioEnable = getGPIORCCEnable(key).reg;
+    unsigned long gpioOffset = getGPIORCCEnable(key).offset;
+
+    *gpioEnable |= (1 << gpioOffset); //Set enable flag
+
+    gpioRegister->MODER &= ~(0b11 << (2 * registerOffset)); //Clear any previous mode
+    gpioRegister->MODER |= (getPinMode(pinMode) << (2 * registerOffset)); //Set mode based on pinmode bit structure
+}
+
+void GPIO::setLow() {
+    auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
+    static_cast<GPIO_TypeDef*>(gpioPeripheral.registers)->ODR &= ~(1 << gpioPeripheral.global_offset);
+}
+
+void GPIO::setHigh() {
+    auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
+    static_cast<GPIO_TypeDef*>(gpioPeripheral.registers)->ODR |= (1 << gpioPeripheral.global_offset);
+}
+
+void GPIO::toggle() {
+    auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
+    static_cast<GPIO_TypeDef*>(gpioPeripheral.registers)->ODR ^= (1 << gpioPeripheral.global_offset);
+}
+
+
+
+GPIO& GPIOManager::get(GPIO_Key key, PinMode pinMode) {
+
+    unsigned int gpioPort = getGPIOPortNumber(key);
+    unsigned long gpioPin = getGPIORegister(key).global_offset; //Use existing structs to get offset
+
+    if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
+        m_gpios[gpioPort][gpioPin] = GPIO(key,pinMode);
+    }
+
+    return m_gpios[gpioPort][gpioPin];
+}

SHAL/Src/Peripheral/Timer/SHAL_TIM.cpp

@@ -2,39 +2,39 @@
 // Created by Luca on 8/28/2025.
 //
 
-#include "Core/Include/Timer/SHAL_TIM.h"
+#include "SHAL_TIM.h"
 #include <cassert>
 
-Timer::Timer(Timer_Key t) : timer(t), timer_reg(getTimerRegister(t)){
-    RCC_Peripheral rcc = getTimerRCC(timer);
-    *rcc.reg |= rcc.bitmask;
+Timer::Timer(Timer_Key t) : TIMER_KEY(t){
+    SHAL_Peripheral_Register rcc = getTimerRCC(TIMER_KEY);
+    *rcc.reg |= (1 << rcc.offset);
 }
 
-Timer::Timer() : timer(Timer_Key::S_TIM_INVALID), timer_reg(nullptr){
+Timer::Timer() : TIMER_KEY(Timer_Key::S_TIM_INVALID){
 
 }
 
 void Timer::start() {
-    timer_reg->CR1 |= TIM_CR1_CEN;
-    timer_reg->EGR |= TIM_EGR_UG; //load prescaler reg and ARR
+    getTimerRegister(TIMER_KEY)->CR1 |= TIM_CR1_CEN;
+    getTimerRegister(TIMER_KEY)->EGR |= TIM_EGR_UG; //load prescaler reg and ARR
     enableInterrupt();
 }
 
 void Timer::stop() {
-    timer_reg->CR1 &= ~TIM_CR1_CEN;
+    getTimerRegister(TIMER_KEY)->CR1 &= ~TIM_CR1_CEN;
 }
 
 void Timer::setPrescaler(uint16_t presc) {
-    timer_reg->PSC = presc;
+    getTimerRegister(TIMER_KEY)->PSC = presc;
 }
 
 void Timer::setARR(uint16_t arr) {
-    timer_reg->ARR = arr;
+    getTimerRegister(TIMER_KEY)->ARR = arr;
 }
 
 void Timer::enableInterrupt() {
-    timer_reg->DIER |= TIM_DIER_UIE;
-    NVIC_EnableIRQ(getIRQn(timer));
+    getTimerRegister(TIMER_KEY)->DIER |= TIM_DIER_UIE;
+    NVIC_EnableIRQ(getIRQn(TIMER_KEY));
 }
 
 
@@ -46,8 +46,8 @@ Timer &TimerManager::get(Timer_Key timer_key) {
     Timer& selected = timers[static_cast<int>(timer_key)];
 
     //Timer queried is not initialized yet (defaults to invalid)
-    if(selected.timer == Timer_Key::S_TIM_INVALID){
-        timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize timer
+    if(selected.TIMER_KEY == Timer_Key::S_TIM_INVALID){
+        timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
     }
 
     return timers[static_cast<int>(timer_key)];

SHAL/Src/System/system_stm32f0xx.c

@@ -12,7 +12,7 @@
   *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
   *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
+  *                                  TIMER_KEY or configure other parameters.
   *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
@@ -136,7 +136,7 @@ void SystemInit(void)
 /**
    * @brief  Update SystemCoreClock variable according to Clock Register Values.
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
+  *         be used by the user application to setup the SysTick TIMER_KEY or configure
   *         other parameters.
   *
   * @note   Each time the core clock (HCLK) changes, this function must be called

SHAL/Src/main.cpp

@@ -0,0 +1,47 @@
+#include "SHAL.h"
+#include "stm32f0xx.h"
+
+
+GPIO* blueLED = nullptr;
+GPIO* greenLED = nullptr;
+
+extern "C" void EXTI0_1_IRQHandler(void) {
+    if (EXTI->PR & (1 << 0)) {   //Check pending flag
+        EXTI->PR |= (1 << 0);    //Clear it by writing 1
+        greenLED->toggle();
+    }
+}
+
+void tim2Handler(){
+    blueLED->toggle();
+}
+
+int main() {
+    RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
+
+    Timer timer2 = getTimer(Timer_Key::S_TIM2);
+
+    blueLED = &initGPIO(GPIO_Key::A4, PinMode::OUTPUT_MODE);
+    greenLED = &initGPIO(GPIO_Key::A5, PinMode::OUTPUT_MODE);
+
+    timer2.setPrescaler(8000 - 1);
+    timer2.setARR(1500 - 1);
+    timer2.setCallbackFunc(tim2Handler);
+    timer2.start();
+
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; //Enable SYSCFG clock (needed for EXTI)
+
+    SYSCFG->EXTICR[0] &= ~SYSCFG_EXTICR1_EXTI0; //Clear EXTI0 mapping
+    SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PB; //Map PA0 -> EXTI0
+
+    EXTI->IMR |= (1 << 0);   //Unmask EXTI0
+    EXTI->RTSR |= (1 << 0);  //Trigger on rising edge
+
+    NVIC_EnableIRQ(EXTI0_1_IRQn); //EXTI lines 0 and 1 share an IRQ vector
+
+    __enable_irq();
+
+    while (true) {
+    	__WFI();
+    }
+}