32 Commits

Author SHA1 Message Date
Ea-r-th
e822b8d9ec Issue: cannot read core 2025-10-17 12:50:16 -07:00
Ea-r-th
04f79cc543 Finished UART refactor 2025-10-17 02:23:56 -07:00
Ea-r-th
d846897296 Finished timer refactor 2025-10-17 01:16:11 -07:00
Ea-r-th
6c8fa459f8 Finished ADC, updating timer code 2025-10-17 00:59:12 -07:00
Ea-r-th
af21480aff ADC sequence abstracted 2025-10-16 21:34:01 -07:00
Ea-r-th
3561879c24 Continuing ADC port 2025-10-15 16:40:27 -07:00
Ea-r-th
cba6c00562 Added core tools, added ADC abstractions for different registers 2025-10-12 20:53:40 -07:00
Ea-r-th
c76dbee94c Beginning of cross platform support 2025-10-08 23:37:10 -07:00
Ea-r-th
ece09aad0b started switch to new platform 2025-10-04 22:58:01 -07:00
Ea-r-th
59e1003262 Made getADCRegister constexpr 2025-09-22 22:36:06 -07:00
Ea-r-th
3480cba21c Fixes 2025-09-22 22:17:59 -07:00
Ea-r-th
03dcfd6bbe Added analogRead to GPIO 2025-09-22 22:12:57 -07:00
Ea-r-th
8214617e3a ADC basic functionality finished 2025-09-22 19:47:15 -07:00
Ea-r-th
f980e62407 Finished ADC methods 2025-09-22 19:36:19 -07:00
Ea-r-th
9550b1b61d Set up ADC files 2025-09-21 14:01:47 -07:00
Ea-r-th
5b66b044b7 Merge branch 'main' of github.com:lucalizaranzu/Shmingo_HAL 2025-09-18 01:23:12 -07:00
Ea-r-th
05465086c4 Final I2C commit 2025-09-18 01:22:09 -07:00
Luca Lizaranzu
cfda94afc1 Merge pull request #1 from lucalizaranzu/I2C
I2C
2025-09-18 01:21:40 -07:00
Ea-r-th
cb232ea55e I2C tested, main file now contains rough sample for use with DHT20 2025-09-18 01:19:03 -07:00
Ea-r-th
8ce717033a Added timeout wait functions to core 2025-09-17 20:07:17 -07:00
Ea-r-th
75132eb040 Changed I2C init order 2025-09-16 03:07:52 -07:00
Ea-r-th
7b32859c88 Added I2C clock config 2025-09-16 00:38:36 -07:00
Ea-r-th
d4136f0761 Added delay functions 2025-09-15 23:48:16 -07:00
Ea-r-th
b2d10f5e5e Unified all current peripheral implementation syntax with macros 2025-09-15 01:20:33 -07:00
Ea-r-th
25b56f9fcd Finished I2C 2025-09-14 23:06:28 -07:00
Ea-r-th
183be36c64 Beginnings of I2C object functions 2025-09-14 17:27:59 -07:00
Ea-r-th
914fbf5a17 Begin I2C implementation and finalize other changes 2025-09-10 01:53:16 -07:00
Ea-r-th
8f3bd7ebd8 Refactored UART frontent retrieval system 2025-09-10 01:43:11 -07:00
Ea-r-th
2f8ba8d9ee Major refactor for entire system - wrong branch but get over it 2025-09-10 01:20:50 -07:00
Ea-r-th
316edd32d8 Before switch to GPIO functions over raw register manipulation for USART 2025-09-10 00:41:08 -07:00
Ea-r-th
55f03031b3 Added files for I2C 2025-09-09 20:11:17 -07:00
9f1aad028d Added friendly reminder 2025-09-08 02:33:01 -07:00
115 changed files with 22986 additions and 587 deletions

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# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100)
# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
# if (__WATCOMC__ % 10) > 0
# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
# endif
#elif defined(__SUNPRO_C)
# define COMPILER_ID "SunPro"
# if __SUNPRO_C >= 0x5100
/* __SUNPRO_C = 0xVRRP */
# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>12)
# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xFF)
# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF)
# else
/* __SUNPRO_CC = 0xVRP */
# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>8)
# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xF)
# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF)
# endif
#elif defined(__HP_cc)
# define COMPILER_ID "HP"
/* __HP_cc = VVRRPP */
# define COMPILER_VERSION_MAJOR DEC(__HP_cc/10000)
# define COMPILER_VERSION_MINOR DEC(__HP_cc/100 % 100)
# define COMPILER_VERSION_PATCH DEC(__HP_cc % 100)
#elif defined(__DECC)
# define COMPILER_ID "Compaq"
/* __DECC_VER = VVRRTPPPP */
# define COMPILER_VERSION_MAJOR DEC(__DECC_VER/10000000)
# define COMPILER_VERSION_MINOR DEC(__DECC_VER/100000 % 100)
# define COMPILER_VERSION_PATCH DEC(__DECC_VER % 10000)
#elif defined(__IBMC__) && defined(__COMPILER_VER__)
# define COMPILER_ID "zOS"
/* __IBMC__ = VRP */
# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10)
#elif defined(__open_xl__) && defined(__clang__)
# define COMPILER_ID "IBMClang"
# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__)
# define COMPILER_VERSION_MINOR DEC(__open_xl_release__)
# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__)
# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__)
#elif defined(__ibmxl__) && defined(__clang__)
# define COMPILER_ID "XLClang"
# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__)
# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__)
# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__)
# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__)
#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800
# define COMPILER_ID "XL"
/* __IBMC__ = VRP */
# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10)
#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800
# define COMPILER_ID "VisualAge"
/* __IBMC__ = VRP */
# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10)
#elif defined(__NVCOMPILER)
# define COMPILER_ID "NVHPC"
# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__)
# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__)
# if defined(__NVCOMPILER_PATCHLEVEL__)
# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__)
# endif
#elif defined(__PGI)
# define COMPILER_ID "PGI"
# define COMPILER_VERSION_MAJOR DEC(__PGIC__)
# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__)
# if defined(__PGIC_PATCHLEVEL__)
# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__)
# endif
#elif defined(__clang__) && defined(__cray__)
# define COMPILER_ID "CrayClang"
# define COMPILER_VERSION_MAJOR DEC(__cray_major__)
# define COMPILER_VERSION_MINOR DEC(__cray_minor__)
# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__)
# define COMPILER_VERSION_INTERNAL_STR __clang_version__
#elif defined(_CRAYC)
# define COMPILER_ID "Cray"
# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR)
# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR)
#elif defined(__TI_COMPILER_VERSION__)
# define COMPILER_ID "TI"
/* __TI_COMPILER_VERSION__ = VVVRRRPPP */
# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000)
# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000)
# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000)
#elif defined(__CLANG_FUJITSU)
# define COMPILER_ID "FujitsuClang"
# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
# define COMPILER_VERSION_INTERNAL_STR __clang_version__
#elif defined(__FUJITSU)
# define COMPILER_ID "Fujitsu"
# if defined(__FCC_version__)
# define COMPILER_VERSION __FCC_version__
# elif defined(__FCC_major__)
# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
# endif
# if defined(__fcc_version)
# define COMPILER_VERSION_INTERNAL DEC(__fcc_version)
# elif defined(__FCC_VERSION)
# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION)
# endif
#elif defined(__ghs__)
# define COMPILER_ID "GHS"
/* __GHS_VERSION_NUMBER = VVVVRP */
# ifdef __GHS_VERSION_NUMBER
# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100)
# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10)
# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10)
# endif
#elif defined(__TASKING__)
# define COMPILER_ID "Tasking"
# define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000)
# define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100)
# define COMPILER_VERSION_INTERNAL DEC(__VERSION__)
#elif defined(__ORANGEC__)
# define COMPILER_ID "OrangeC"
# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__)
# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__)
# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__)
#elif defined(__TINYC__)
# define COMPILER_ID "TinyCC"
#elif defined(__BCC__)
# define COMPILER_ID "Bruce"
#elif defined(__SCO_VERSION__)
# define COMPILER_ID "SCO"
#elif defined(__ARMCC_VERSION) && !defined(__clang__)
# define COMPILER_ID "ARMCC"
#if __ARMCC_VERSION >= 1000000
/* __ARMCC_VERSION = VRRPPPP */
# define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000)
# define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100)
# define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
#else
/* __ARMCC_VERSION = VRPPPP */
# define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
# define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
# define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
#endif
#elif defined(__clang__) && defined(__apple_build_version__)
# define COMPILER_ID "AppleClang"
# if defined(_MSC_VER)
# define SIMULATE_ID "MSVC"
# endif
# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
# if defined(_MSC_VER)
/* _MSC_VER = VVRR */
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
# endif
# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
# define COMPILER_ID "ARMClang"
# define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
# define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
# define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100 % 100)
# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
#elif defined(__clang__) && defined(__ti__)
# define COMPILER_ID "TIClang"
# define COMPILER_VERSION_MAJOR DEC(__ti_major__)
# define COMPILER_VERSION_MINOR DEC(__ti_minor__)
# define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__)
# define COMPILER_VERSION_INTERNAL DEC(__ti_version__)
#elif defined(__clang__)
# define COMPILER_ID "Clang"
# if defined(_MSC_VER)
# define SIMULATE_ID "MSVC"
# endif
# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
# if defined(_MSC_VER)
/* _MSC_VER = VVRR */
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
# endif
#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__))
# define COMPILER_ID "LCC"
# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100)
# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100)
# if defined(__LCC_MINOR__)
# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__)
# endif
# if defined(__GNUC__) && defined(__GNUC_MINOR__)
# define SIMULATE_ID "GNU"
# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
# if defined(__GNUC_PATCHLEVEL__)
# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
# endif
# endif
#elif defined(__GNUC__)
# define COMPILER_ID "GNU"
# define COMPILER_VERSION_MAJOR DEC(__GNUC__)
# if defined(__GNUC_MINOR__)
# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
# endif
# if defined(__GNUC_PATCHLEVEL__)
# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
# endif
#elif defined(_MSC_VER)
# define COMPILER_ID "MSVC"
/* _MSC_VER = VVRR */
# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
# if defined(_MSC_FULL_VER)
# if _MSC_VER >= 1400
/* _MSC_FULL_VER = VVRRPPPPP */
# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
# else
/* _MSC_FULL_VER = VVRRPPPP */
# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
# endif
# endif
# if defined(_MSC_BUILD)
# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
# endif
#elif defined(_ADI_COMPILER)
# define COMPILER_ID "ADSP"
#if defined(__VERSIONNUM__)
/* __VERSIONNUM__ = 0xVVRRPPTT */
# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF)
# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF)
# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF)
# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF)
#endif
#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
# define COMPILER_ID "IAR"
# if defined(__VER__) && defined(__ICCARM__)
# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__))
# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
# endif
#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC)
# define COMPILER_ID "SDCC"
# if defined(__SDCC_VERSION_MAJOR)
# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR)
# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR)
# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH)
# else
/* SDCC = VRP */
# define COMPILER_VERSION_MAJOR DEC(SDCC/100)
# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10)
# define COMPILER_VERSION_PATCH DEC(SDCC % 10)
# endif
/* These compilers are either not known or too old to define an
identification macro. Try to identify the platform and guess that
it is the native compiler. */
#elif defined(__hpux) || defined(__hpua)
# define COMPILER_ID "HP"
#else /* unknown compiler */
# define COMPILER_ID ""
#endif
/* Construct the string literal in pieces to prevent the source from
getting matched. Store it in a pointer rather than an array
because some compilers will just produce instructions to fill the
array rather than assigning a pointer to a static array. */
char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
#ifdef SIMULATE_ID
char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
#endif
#ifdef __QNXNTO__
char const* qnxnto = "INFO" ":" "qnxnto[]";
#endif
#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
#endif
#define STRINGIFY_HELPER(X) #X
#define STRINGIFY(X) STRINGIFY_HELPER(X)
/* Identify known platforms by name. */
#if defined(__linux) || defined(__linux__) || defined(linux)
# define PLATFORM_ID "Linux"
#elif defined(__MSYS__)
# define PLATFORM_ID "MSYS"
#elif defined(__CYGWIN__)
# define PLATFORM_ID "Cygwin"
#elif defined(__MINGW32__)
# define PLATFORM_ID "MinGW"
#elif defined(__APPLE__)
# define PLATFORM_ID "Darwin"
#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
# define PLATFORM_ID "Windows"
#elif defined(__FreeBSD__) || defined(__FreeBSD)
# define PLATFORM_ID "FreeBSD"
#elif defined(__NetBSD__) || defined(__NetBSD)
# define PLATFORM_ID "NetBSD"
#elif defined(__OpenBSD__) || defined(__OPENBSD)
# define PLATFORM_ID "OpenBSD"
#elif defined(__sun) || defined(sun)
# define PLATFORM_ID "SunOS"
#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
# define PLATFORM_ID "AIX"
#elif defined(__hpux) || defined(__hpux__)
# define PLATFORM_ID "HP-UX"
#elif defined(__HAIKU__)
# define PLATFORM_ID "Haiku"
#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
# define PLATFORM_ID "BeOS"
#elif defined(__QNX__) || defined(__QNXNTO__)
# define PLATFORM_ID "QNX"
#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
# define PLATFORM_ID "Tru64"
#elif defined(__riscos) || defined(__riscos__)
# define PLATFORM_ID "RISCos"
#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
# define PLATFORM_ID "SINIX"
#elif defined(__UNIX_SV__)
# define PLATFORM_ID "UNIX_SV"
#elif defined(__bsdos__)
# define PLATFORM_ID "BSDOS"
#elif defined(_MPRAS) || defined(MPRAS)
# define PLATFORM_ID "MP-RAS"
#elif defined(__osf) || defined(__osf__)
# define PLATFORM_ID "OSF1"
#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv)
# define PLATFORM_ID "SCO_SV"
#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
# define PLATFORM_ID "ULTRIX"
#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
# define PLATFORM_ID "Xenix"
#elif defined(__WATCOMC__)
# if defined(__LINUX__)
# define PLATFORM_ID "Linux"
# elif defined(__DOS__)
# define PLATFORM_ID "DOS"
# elif defined(__OS2__)
# define PLATFORM_ID "OS2"
# elif defined(__WINDOWS__)
# define PLATFORM_ID "Windows3x"
# elif defined(__VXWORKS__)
# define PLATFORM_ID "VxWorks"
# else /* unknown platform */
# define PLATFORM_ID
# endif
#elif defined(__INTEGRITY)
# if defined(INT_178B)
# define PLATFORM_ID "Integrity178"
# else /* regular Integrity */
# define PLATFORM_ID "Integrity"
# endif
# elif defined(_ADI_COMPILER)
# define PLATFORM_ID "ADSP"
#else /* unknown platform */
# define PLATFORM_ID
#endif
/* For windows compilers MSVC and Intel we can determine
the architecture of the compiler being used. This is because
the compilers do not have flags that can change the architecture,
but rather depend on which compiler is being used
*/
#if defined(_WIN32) && defined(_MSC_VER)
# if defined(_M_IA64)
# define ARCHITECTURE_ID "IA64"
# elif defined(_M_ARM64EC)
# define ARCHITECTURE_ID "ARM64EC"
# elif defined(_M_X64) || defined(_M_AMD64)
# define ARCHITECTURE_ID "x64"
# elif defined(_M_IX86)
# define ARCHITECTURE_ID "X86"
# elif defined(_M_ARM64)
# define ARCHITECTURE_ID "ARM64"
# elif defined(_M_ARM)
# if _M_ARM == 4
# define ARCHITECTURE_ID "ARMV4I"
# elif _M_ARM == 5
# define ARCHITECTURE_ID "ARMV5I"
# else
# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
# endif
# elif defined(_M_MIPS)
# define ARCHITECTURE_ID "MIPS"
# elif defined(_M_SH)
# define ARCHITECTURE_ID "SHx"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
# endif
#elif defined(__WATCOMC__)
# if defined(_M_I86)
# define ARCHITECTURE_ID "I86"
# elif defined(_M_IX86)
# define ARCHITECTURE_ID "X86"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
# endif
#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
# if defined(__ICCARM__)
# define ARCHITECTURE_ID "ARM"
# elif defined(__ICCRX__)
# define ARCHITECTURE_ID "RX"
# elif defined(__ICCRH850__)
# define ARCHITECTURE_ID "RH850"
# elif defined(__ICCRL78__)
# define ARCHITECTURE_ID "RL78"
# elif defined(__ICCRISCV__)
# define ARCHITECTURE_ID "RISCV"
# elif defined(__ICCAVR__)
# define ARCHITECTURE_ID "AVR"
# elif defined(__ICC430__)
# define ARCHITECTURE_ID "MSP430"
# elif defined(__ICCV850__)
# define ARCHITECTURE_ID "V850"
# elif defined(__ICC8051__)
# define ARCHITECTURE_ID "8051"
# elif defined(__ICCSTM8__)
# define ARCHITECTURE_ID "STM8"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
# endif
#elif defined(__ghs__)
# if defined(__PPC64__)
# define ARCHITECTURE_ID "PPC64"
# elif defined(__ppc__)
# define ARCHITECTURE_ID "PPC"
# elif defined(__ARM__)
# define ARCHITECTURE_ID "ARM"
# elif defined(__x86_64__)
# define ARCHITECTURE_ID "x64"
# elif defined(__i386__)
# define ARCHITECTURE_ID "X86"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
# endif
#elif defined(__clang__) && defined(__ti__)
# if defined(__ARM_ARCH)
# define ARCHITECTURE_ID "Arm"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
# endif
#elif defined(__TI_COMPILER_VERSION__)
# if defined(__TI_ARM__)
# define ARCHITECTURE_ID "ARM"
# elif defined(__MSP430__)
# define ARCHITECTURE_ID "MSP430"
# elif defined(__TMS320C28XX__)
# define ARCHITECTURE_ID "TMS320C28x"
# elif defined(__TMS320C6X__) || defined(_TMS320C6X)
# define ARCHITECTURE_ID "TMS320C6x"
# else /* unknown architecture */
# define ARCHITECTURE_ID ""
# endif
# elif defined(__ADSPSHARC__)
# define ARCHITECTURE_ID "SHARC"
# elif defined(__ADSPBLACKFIN__)
# define ARCHITECTURE_ID "Blackfin"
#elif defined(__TASKING__)
# if defined(__CTC__) || defined(__CPTC__)
# define ARCHITECTURE_ID "TriCore"
# elif defined(__CMCS__)
# define ARCHITECTURE_ID "MCS"
# elif defined(__CARM__)
# define ARCHITECTURE_ID "ARM"
# elif defined(__CARC__)
# define ARCHITECTURE_ID "ARC"
# elif defined(__C51__)
# define ARCHITECTURE_ID "8051"
# elif defined(__CPCP__)
# define ARCHITECTURE_ID "PCP"
# else
# define ARCHITECTURE_ID ""
# endif
#else
# define ARCHITECTURE_ID
#endif
/* Convert integer to decimal digit literals. */
#define DEC(n) \
('0' + (((n) / 10000000)%10)), \
('0' + (((n) / 1000000)%10)), \
('0' + (((n) / 100000)%10)), \
('0' + (((n) / 10000)%10)), \
('0' + (((n) / 1000)%10)), \
('0' + (((n) / 100)%10)), \
('0' + (((n) / 10)%10)), \
('0' + ((n) % 10))
/* Convert integer to hex digit literals. */
#define HEX(n) \
('0' + ((n)>>28 & 0xF)), \
('0' + ((n)>>24 & 0xF)), \
('0' + ((n)>>20 & 0xF)), \
('0' + ((n)>>16 & 0xF)), \
('0' + ((n)>>12 & 0xF)), \
('0' + ((n)>>8 & 0xF)), \
('0' + ((n)>>4 & 0xF)), \
('0' + ((n) & 0xF))
/* Construct a string literal encoding the version number. */
#ifdef COMPILER_VERSION
char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]";
/* Construct a string literal encoding the version number components. */
#elif defined(COMPILER_VERSION_MAJOR)
char const info_version[] = {
'I', 'N', 'F', 'O', ':',
'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[',
COMPILER_VERSION_MAJOR,
# ifdef COMPILER_VERSION_MINOR
'.', COMPILER_VERSION_MINOR,
# ifdef COMPILER_VERSION_PATCH
'.', COMPILER_VERSION_PATCH,
# ifdef COMPILER_VERSION_TWEAK
'.', COMPILER_VERSION_TWEAK,
# endif
# endif
# endif
']','\0'};
#endif
/* Construct a string literal encoding the internal version number. */
#ifdef COMPILER_VERSION_INTERNAL
char const info_version_internal[] = {
'I', 'N', 'F', 'O', ':',
'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_',
'i','n','t','e','r','n','a','l','[',
COMPILER_VERSION_INTERNAL,']','\0'};
#elif defined(COMPILER_VERSION_INTERNAL_STR)
char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]";
#endif
/* Construct a string literal encoding the version number components. */
#ifdef SIMULATE_VERSION_MAJOR
char const info_simulate_version[] = {
'I', 'N', 'F', 'O', ':',
's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[',
SIMULATE_VERSION_MAJOR,
# ifdef SIMULATE_VERSION_MINOR
'.', SIMULATE_VERSION_MINOR,
# ifdef SIMULATE_VERSION_PATCH
'.', SIMULATE_VERSION_PATCH,
# ifdef SIMULATE_VERSION_TWEAK
'.', SIMULATE_VERSION_TWEAK,
# endif
# endif
# endif
']','\0'};
#endif
/* Construct the string literal in pieces to prevent the source from
getting matched. Store it in a pointer rather than an array
because some compilers will just produce instructions to fill the
array rather than assigning a pointer to a static array. */
char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]";
char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]";
#define C_STD_99 199901L
#define C_STD_11 201112L
#define C_STD_17 201710L
#define C_STD_23 202311L
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Copyright (C) Microsoft Corporation. All rights reserved.
cl : Command line warning D9002 : ignoring unknown option '--version'
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cl : Command line warning D9002 : ignoring unknown option '--version'
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message: |
Checking whether the ASM compiler is ARMClang using "--version" did not match "armclang":
Microsoft (R) C/C++ Optimizing Compiler Version 19.38.33145 for x64
Copyright (C) Microsoft Corporation. All rights reserved.
cl : Command line warning D9002 : ignoring unknown option '--version'
cl : Command line error D8003 : missing source filename
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Checking whether the ASM compiler is OrangeC using "--version" did not match "occ \\(OrangeC\\) Version":
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cl : Command line warning D9002 : ignoring unknown option '--version'
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- "CMakeLists.txt:17 (enable_language)"
message: |
Checking whether the ASM compiler is HP using "-V" did not match "HP C":
Microsoft (R) C/C++ Optimizing Compiler Version 19.38.33145 for x64
Copyright (C) Microsoft Corporation. All rights reserved.
cl : Command line error D8004 : '/V' requires an argument
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message: |
Checking whether the ASM compiler is Intel using "--version" did not match "(ICC)":
Microsoft (R) C/C++ Optimizing Compiler Version 19.38.33145 for x64
Copyright (C) Microsoft Corporation. All rights reserved.
cl : Command line warning D9002 : ignoring unknown option '--version'
cl : Command line error D8003 : missing source filename
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backtrace:
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- "CMakeLists.txt:17 (enable_language)"
message: |
Checking whether the ASM compiler is IntelLLVM using "--version" did not match "(Intel[^
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Microsoft (R) C/C++ Optimizing Compiler Version 19.38.33145 for x64
Copyright (C) Microsoft Corporation. All rights reserved.
cl : Command line warning D9002 : ignoring unknown option '--version'
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message: |
Checking whether the ASM compiler is SunPro using "-V" did not match "Sun C":
Microsoft (R) C/C++ Optimizing Compiler Version 19.38.33145 for x64
Copyright (C) Microsoft Corporation. All rights reserved.
cl : Command line error D8004 : '/V' requires an argument
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kind: "message-v1"
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- "CMakeLists.txt:17 (enable_language)"
message: |
Checking whether the ASM compiler is XL using "-qversion" did not match "XL C":
Microsoft (R) C/C++ Optimizing Compiler Version 19.38.33145 for x64
Copyright (C) Microsoft Corporation. All rights reserved.
cl : Command line warning D9002 : ignoring unknown option '-qversion'
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backtrace:
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- "CMakeLists.txt:17 (enable_language)"
message: |
Checking whether the ASM compiler is MSVC using "-?" matched "Microsoft":
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Copyright (C) Microsoft Corporation. All rights reserved.
C/C++ COMPILER OPTIONS
-OPTIMIZATION-
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/Ox optimizations (favor speed)
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blend - a combination of optimizations for several different x64 processors
AMD64 - 64-bit AMD processors
INTEL64 - Intel(R)64 architecture processors
ATOM - Intel(R) Atom(TM) processors
-CODE GENERATION-
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except[-] - consider floating-point exceptions when generating code
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precise - "precise" floating-point model; results are predictable
strict - "strict" floating-point model (implies /fp:except)
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ms - Acquire/release semantics guaranteed on volatile accesses
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BC - results compatible with VS2017 and earlier compiler
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c++17 - ISO/IEC 14882:2017
c++20 - ISO/IEC 14882:2020
c++latest - latest draft standard (feature set subject to change)
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wchar_t[-] wchar_t is the native type, not a typedef
auto[-] enforce the new Standard C++ meaning for auto
trigraphs[-] enable trigraphs (off by default)
rvalueCast[-] enforce Standard C++ explicit type conversion rules
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conversion (off by default)
implicitNoexcept[-] enable implicit noexcept on required functions
threadSafeInit[-] enable thread-safe local static initialization
inline[-] remove unreferenced function or data if it is
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functions (on by default)
throwingNew[-] assume operator new throws on failure (off by default)
referenceBinding[-] a temporary will not bind to an non-const
lvalue reference (off by default)
twoPhase- disable two-phase name lookup
ternary[-] enforce C++11 rules for conditional operator (off by default)
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alignedNew[-] enable C++17 alignment of dynamically allocated objects (on by default)
hiddenFriend[-] enforce Standard C++ hidden friend rules (implied by /permissive-)
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lambda[-] better lambda support by using the newer lambda processor (off by default)
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zeroSizeArrayNew[-] call member new/delete for 0-size arrays of objects (on by default)
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gotoScope[-] cannot jump past the initialization of a variable (implied by /permissive-)
templateScope[-] enforce Standard C++ template parameter shadowing rules
enumTypes[-] enable Standard C++ underlying enum types (off by default)
checkGwOdr[-] enforce Standard C++ one definition rule violations
when /Gw has been enabled (off by default)
__STDC__ define __STDC__ to 1 in C
/await enable resumable functions extension
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/constexpr:depth<N> recursion depth limit for constexpr evaluation (default: 512)
/constexpr:backtrace<N> show N constexpr evaluations in diagnostics (default: 10)
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/vd{0|1|2} disable/enable vtordisp /vm<x> type of pointers to members
/std:<c11|c17> C standard version
c11 - ISO/IEC 9899:2011
c17 - ISO/IEC 9899:2018
/ZI enable Edit and Continue debug info
/openmp enable OpenMP 2.0 language extensions
/openmp:experimental enable OpenMP 2.0 language extensions plus select OpenMP 3.0+ language extensions
/openmp:llvm OpenMP language extensions using LLVM runtime
-MISCELLANEOUS-
@<file> options response file /?, /help print this help message
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/errorReport:option deprecated. Report internal compiler errors to Microsoft
none - do not send report
prompt - prompt to immediately send report
queue - at next admin logon, prompt to send report (default)
send - send report automatically
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/J default char type is unsigned
/MP[n] use up to 'n' processes for compilation
/nologo suppress copyright message /showIncludes show include file names
/Tc<source file> compile file as .c /Tp<source file> compile file as .cpp
/TC compile all files as .c /TP compile all files as .cpp
/V<string> set version string /Yc[file] create .PCH file
/Yd put debug info in every .OBJ /Yl[sym] inject .PCH ref for debug lib
/Yu[file] use .PCH file /Y- disable all PCH options
/Zm<n> max memory alloc (% of default) /FS force to use MSPDBSRV.EXE
/source-charset:<iana-name>|.nnnn set source character set
/execution-charset:<iana-name>|.nnnn set execution character set
/utf-8 set source and execution character set to UTF-8
/validate-charset[-] validate UTF-8 files for only legal characters
/fastfail[-] enable fast-fail mode /JMC[-] enable native just my code
/presetPadding[-] zero initialize padding for stack based class types
/volatileMetadata[-] generate metadata on volatile memory accesses
/sourcelink [file] file containing source link information
-LINKING-
/LD Create .DLL /LDd Create .DLL debug library
/LN Create a .netmodule /F<num> set stack size
/link [linker options and libraries] /MD link with MSVCRT.LIB
/MT link with LIBCMT.LIB /MDd link with MSVCRTD.LIB debug lib
/MTd link with LIBCMTD.LIB debug lib
-CODE ANALYSIS-
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/analyze:log<name> Warnings to file /analyze:autolog Log to *.pftlog
/analyze:autolog:ext<ext> Log to *.<ext>/analyze:autolog- No log file
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/analyze:max_paths<num> Max paths /analyze:only Analyze, no code gen
-DIAGNOSTICS-
/diagnostics:<args,...> controls the format of diagnostic messages:
classic - retains prior format
column[-] - prints column information
caret[-] - prints column and the indicated line of source
/Wall enable all warnings /w disable all warnings
/W<n> set warning level (default n=1)
/Wv:xx[.yy[.zzzzz]] disable warnings introduced after version xx.yy.zzzzz
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/wo<n> issue warning n once /w<l><n> set warning level 1-4 for n
/external:I <path> - location of external headers
/external:env:<var> - environment variable with locations of external headers
/external:anglebrackets - treat all headers included via <> as external
/external:W<n> - warning level for external headers
/external:templates[-] - evaluate warning level across template instantiation chain
/sdl enable additional security features and warnings
/options:strict unrecognized compiler options are an error
...

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@@ -3,15 +3,15 @@ cmake_minimum_required(VERSION 3.19)
project(shmingo-HAL)
set(PROJECT_DIR ${CMAKE_CURRENT_SOURCE_DIR})
set(MCU_FAMILY "STM32F0xx" CACHE STRING "MCU family")
set(MCU_MODEL "" CACHE STRING "MCU model")
set(MCU_FAMILY "STM32L4xx" CACHE STRING "MCU family")
set(MCU_MODEL "STM32L432xx" CACHE STRING "MCU model")
set(CPU_PARAMETERS
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-mthumb)
set(STARTUP_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/startup_stm32f072rbtx.s)
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set(STARTUP_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/L432KC/startup_stm32l432kcux.s)
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set(EXECUTABLE ${CMAKE_PROJECT_NAME})
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@@ -36,13 +36,21 @@ set(PROJECT_INCLUDE_DIRECTORIES
SHAL/Include/Peripheral/GPIO/Reg
SHAL/Include/Peripheral/UART
SHAL/Include/Peripheral/UART/Reg
SHAL/Include/Peripheral/I2C
SHAL/Include/Peripheral/I2C/Reg
SHAL/Include/Peripheral/ADC
SHAL/Include/Peripheral/ADC/Reg
SHAL/Include/Peripheral/EXT/
SHAL/Include/Peripheral/EXT/Reg
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include
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${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/Universal/*.c
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/Universal/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/main.cpp
)
add_executable(${EXECUTABLE}
@@ -65,6 +73,8 @@ target_compile_options(${EXECUTABLE} PRIVATE
-Wextra
-Wpedantic
-Wno-unused-parameter
-Wno-switch
-Wno-implicit-fallthrough
$<$<COMPILE_LANGUAGE:CXX>:
-Wno-volatile
-Wsuggest-override>

View File

@@ -369,16 +369,16 @@ typedef struct
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
__IO uint32_t MODER; /*!< SHAL_GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< SHAL_GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< SHAL_GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< SHAL_GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< SHAL_GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< SHAL_GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< SHAL_GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< SHAL_GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< SHAL_GPIO alternate function low register, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< SHAL_GPIO bit reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
@@ -6490,7 +6490,7 @@ typedef struct
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* General Purpose IOs (SHAL_GPIO) */
/* */
/******************************************************************************/
/******************* Bit definition for GPIO_MODER register *****************/
@@ -10933,7 +10933,7 @@ typedef struct
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7))
/****************************** GPIO Instances ********************************/
/****************************** SHAL_GPIO Instances ********************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
@@ -10941,14 +10941,14 @@ typedef struct
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF))
/**************************** GPIO Alternate Function Instances ***************/
/**************************** SHAL_GPIO Alternate Function Instances ***************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE))
/****************************** GPIO Lock Instances ***************************/
/****************************** SHAL_GPIO Lock Instances ***************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB))
@@ -11192,11 +11192,11 @@ typedef struct
/****************************** TSC Instances *********************************/
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
/*********************** UART Instances : IRDA mode ***************************/
/*********************** SHAL_UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/********************* UART Instances : Smard card mode ***********************/
/********************* SHAL_UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
@@ -11210,35 +11210,35 @@ typedef struct
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/******************** UART Instances : Asynchronous mode **********************/
/******************** SHAL_UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/******************** UART Instances : Half-Duplex mode **********************/
/******************** SHAL_UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/****************** UART Instances : Hardware Flow control ********************/
/****************** SHAL_UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/****************** UART Instances : LIN mode ********************/
/****************** SHAL_UART Instances : LIN mode ********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/****************** UART Instances : wakeup from stop mode ********************/
/****************** SHAL_UART Instances : wakeup from stop mode ********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/* Old macro definition maintained for legacy purpose */
#define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE
/****************** UART Instances : Driver enable detection ********************/
/****************** SHAL_UART Instances : Driver enable detection ********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,303 @@
/**
******************************************************************************
* @file stm32l4xx.h
* @author MCD Application Team
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32L4xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx
* @{
*/
#ifndef __STM32L4xx_H
#define __STM32L4xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32L4)
#define STM32L4
#endif /* STM32L4 */
/* Uncomment the line below according to the target STM32L4 device used in your
application
*/
#if !defined (STM32L412xx) && !defined (STM32L422xx) && \
!defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L496xx) && !defined (STM32L4A6xx) && \
!defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \
!defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
/* #define STM32L412xx */ /*!< STM32L412xx Devices */
/* #define STM32L422xx */ /*!< STM32L422xx Devices */
/* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */
/* #define STM32L442xx */ /*!< STM32L442xx Devices */
/* #define STM32L443xx */ /*!< STM32L443xx Devices */
/* #define STM32L451xx */ /*!< STM32L451xx Devices */
/* #define STM32L452xx */ /*!< STM32L452xx Devices */
/* #define STM32L462xx */ /*!< STM32L462xx Devices */
/* #define STM32L471xx */ /*!< STM32L471xx Devices */
/* #define STM32L475xx */ /*!< STM32L475xx Devices */
/* #define STM32L476xx */ /*!< STM32L476xx Devices */
/* #define STM32L485xx */ /*!< STM32L485xx Devices */
/* #define STM32L486xx */ /*!< STM32L486xx Devices */
/* #define STM32L496xx */ /*!< STM32L496xx Devices */
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
/* #define STM32L4P5xx */ /*!< STM32L4Q5xx Devices */
/* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */
/* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */
/* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */
/* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */
/* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */
/* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L4_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#include "stm32l4s9xx.h"
#else
#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32l4xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32L4xx_H */
/**
* @}
*/
/**
* @}
*/

View File

@@ -0,0 +1,106 @@
/**
******************************************************************************
* @file system_stm32l4xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32L4XX_H
#define __SYSTEM_STM32L4XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32L4xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32L4XX_H */
/**
* @}
*/
/**
* @}
*/

View File

@@ -0,0 +1,189 @@
/*
******************************************************************************
**
** @file : LinkerScript.ld
**
** @author : Auto-generated by STM32CubeIDE
**
** Abstract : Linker script for NUCLEO-L432KC Board embedding STM32L432KCUx Device from stm32l4 series
** 256KBytes FLASH
** 48KBytes RAM
** 16KBytes RAM2
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
******************************************************************************
** @attention
**
** Copyright (c) 2025 STMicroelectronics.
** All rights reserved.
**
** This software is licensed under terms that can be found in the LICENSE file
** in the root directory of this software component.
** If no LICENSE file comes with this software, it is provided AS-IS.
**
******************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Memories definition */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K
RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 16K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K
}
/* Sections */
SECTIONS
{
/* The startup code into "FLASH" Rom type memory */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data into "FLASH" Rom type memory */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data into "FLASH" Rom type memory */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
} >FLASH
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
. = ALIGN(4);
} >FLASH
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
/* Used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections into "RAM" Ram type memory */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
*(.RamFunc) /* .RamFunc sections */
*(.RamFunc*) /* .RamFunc* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section into "RAM" Ram type memory */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the compiler libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

View File

@@ -0,0 +1,449 @@
/**
******************************************************************************
* @file startup_stm32l432xx.s
* @author MCD Application Team
* @brief STM32L432xx devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word 0
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word 0
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word 0
.word COMP_IRQHandler
.word LPTIM1_IRQHandler
.word LPTIM2_IRQHandler
.word USB_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word LPUART1_IRQHandler
.word QUADSPI_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word SAI1_IRQHandler
.word 0
.word SWPMI1_IRQHandler
.word TSC_IRQHandler
.word 0
.word 0
.word RNG_IRQHandler
.word FPU_IRQHandler
.word CRS_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak USB_IRQHandler
.thumb_set USB_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler

View File

@@ -6,8 +6,8 @@ BUILD_TYPE ?= Debug
TOOLCHAIN := gcc-arm-none-eabi.cmake
# MCU target (override on command line: make build MCU_MODEL=STM32F051x8)
MCU_MODEL ?= STM32F072xB
MCU_FAMILY ?= STM32F0xx
MCU_MODEL ?= STM32L432xx
MCU_FAMILY ?= STM32L4xx
# --- Default target ---
all: build

View File

@@ -11,10 +11,88 @@
#include <cstdint>
//Overall init function for SHAL --------------------------
void SHAL_init();
//---------------------------------------------------------
//Universal structs and defines ---------------------------
enum class SHAL_Result{
OKAY,
ERROR
};
#define SHAL_CALL(func) \
if(func != SHAL_Result::OKAY){ \
return SHAL_Result::ERROR; \
}
#define SHAL_WAIT_FOR_CONDITION_US(cond, timeout_us) \
SHAL_wait_for_condition_us([&](){ return (cond); }, (timeout_us))
#define SHAL_WAIT_FOR_CONDITION_MS(cond, timeout_ms) \
SHAL_wait_for_condition_ms([&](){ return (cond); }, (timeout_ms))
//Currently configures systick to count down in microseconds
void systick_init();
//Max of 16ms, use SHAL_delay_ms for longer delay
void SHAL_delay_us(uint32_t us);
void SHAL_delay_ms(uint32_t ms);
template<typename Condition>
bool SHAL_wait_for_condition_us(Condition cond, uint32_t timeout_us) {
while (timeout_us--) {
if (cond()) {
return true; // success
}
SHAL_delay_us(1);
}
return false; // timeout
}
template<typename Condition>
bool SHAL_wait_for_condition_ms(Condition cond, uint32_t timeout_ms) {
while (timeout_ms--) {
if (cond()) {
return true; // success
}
SHAL_delay_ms(1);
}
return false; // timeout
}
//Sets bits starting from offset as the LSB
static inline void SHAL_set_bits(volatile uint32_t* reg, uint32_t size, uint32_t bits, uint32_t offset){
uint32_t mask = (1 << (size)) - 1;
*reg &= ~(mask << offset);
*reg |= bits << offset;
}
//Sets bits starting from offset as the LSB (for uint16_t)
static inline void SHAL_set_bits_16(volatile uint16_t* reg, uint32_t size, uint32_t bits, uint32_t offset){
uint16_t mask = (1 << (size)) - 1;
*reg &= ~(mask << offset);
*reg |= bits << offset;
}
static inline void SHAL_clear_bitmask(volatile uint32_t* reg, uint32_t mask){
*reg &= ~(mask);
}
static inline void SHAL_apply_bitmask(volatile uint32_t* reg, uint32_t mask){
SHAL_clear_bitmask(reg,mask);
*reg |= mask;
}
//---------------------------------------------------------
@@ -50,10 +128,59 @@
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#error "Please select first the target STM32 device used in your application (in stm32f0xx.h file)"
#endif

View File

@@ -0,0 +1,31 @@
//
// Created by Luca on 9/21/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_REG_F072XB_H
#define SHMINGO_HAL_SHAL_ADC_REG_F072XB_H
#include "SHAL_CORE.h"
#include "SHAL_ADC_TYPES.h"
#define SHAL_ADC1 SHAL_ADC(1)
enum class ADC_Key : uint8_t{
S_ADC1,
NUM_ADC,
INVALID
};
constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
switch(key){
case ADC_Key::S_ADC1:
return ADC1;
case ADC_Key::NUM_ADC:
case ADC_Key::INVALID:
return nullptr;
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_ADC_REG_F072XB_H

View File

@@ -0,0 +1,173 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_REG_L432KC_H
#define SHMINGO_HAL_SHAL_ADC_REG_L432KC_H
#include "SHAL_CORE.h"
#include "SHAL_ADC_TYPES.h"
#define SHAL_ADC1 SHAL_ADC(1)
#define NUM_ADCS 1
#define NUM_ADC_CHANNELS 16
enum class SHAL_ADC_Channel : uint32_t {
CH0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
CH8,
CH9,
CH10,
CH11,
CH12,
CH13,
CH14,
CH15,
CHTemp,
CHRef,
CHBat
};
enum class ADC_Key : uint8_t{
S_ADC1 = 0,
NUM_ADC = 1,
INVALID = 255
};
enum class ADC_Clock_Source : uint8_t {
SHAL_SYSCLK,
SHAL_PLLSAI1,
SHAL_PLL,
SHAL_MSI
};
static volatile ADC_TypeDef* ADC_TABLE[1] = { //Lookup table for ADCs
ADC1,
};
static inline SHAL_ADC_Common_Control_Reg getADCCommonControl() {
return {&ADC1_COMMON->CCR ,ADC_CCR_VREFEN,ADC_CCR_TSEN,ADC_CCR_VBATEN};
}
static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
SHAL_ADC_RCC_Enable_Reg res = {nullptr, RCC_AHB2ENR_ADCEN};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN, ADC_CR_ADDIS, ADC_CR_ADCAL, ADC_CR_ADSTART};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
return res;
}
static inline SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
SHAL_ADC_Config_Reg res = {nullptr, ADC_CFGR_CONT, ADC_CFGR_RES_Pos, ADC_CFGR_ALIGN_Pos};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CFGR);
return res;
}
static inline SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
SHAL_ADC_ISR_Reg res = {nullptr, ADC_ISR_EOC, ADC_ISR_EOS, ADC_ISR_ADRDY};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
return res;
}
static inline SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Msk, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
switch(clockSource){
case ADC_Clock_Source::SHAL_PLLSAI1:
res.mask = 1U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_PLL:
res.mask = 2U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_SYSCLK:
res.mask = 3U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_MSI:
break; //TODO implement this
}
return res;
}
static inline SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* SMPReg = nullptr;
uint32_t pos;
auto channelNum = static_cast<uint8_t>(channel);
if (channelNum <= 9) {
SMPReg = &ADCReg->SQR1;
pos = (channelNum * 3);
} else {
SMPReg = &ADCReg->SQR2;
pos = ((channelNum - 10) * 3);
}
return {SMPReg, pos};
}
static inline SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
return res;
}
static inline SHAL_ADC_Sequence_Reg getADCSequenceRegisters(ADC_Key key){
volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];
SHAL_ADC_Sequence_Reg res = {{&adc_reg->SQR1,
&adc_reg->SQR2,
&adc_reg->SQR3,
&adc_reg->SQR4,
nullptr,
nullptr},
{1UL << 0,
1UL << 6,
1UL << 12,
1UL << 18,
1UL << 24}
};
return res;
}
constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
switch(key){
case ADC_Key::S_ADC1:
return ADC1;
case ADC_Key::NUM_ADC:
case ADC_Key::INVALID:
return nullptr;
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_ADC_REG_L432KC_H

View File

@@ -0,0 +1,92 @@
//
// Created by Luca on 9/21/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_H
#define SHMINGO_HAL_SHAL_ADC_H
#include <cstdint>
#include "SHAL_CORE.h"
#include "SHAL_ADC_REG.h"
class SHAL_ADC {
friend class ADCManager;
public:
SHAL_Result init();
SHAL_Result calibrate();
SHAL_Result configureResolution(SHAL_ADC_Resolution resolution);
SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment);
/// Performs analog to digital conversion on a single channel, one time
/// \param channel Channel to be converted
/// \param time SHAL_ADC_SampleTime - amount of clock cycles per conversion
/// \return resulting value
uint16_t singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8);
/// Performs analog to digital conversion on multiple channels, one time
/// \param channels Pointer to an array of channels to convert
/// \param numChannels Number of channels to convert
/// \param result Pointer to store converted channel results in
/// \param time SHAL_ADC_SampleTime - amount of clock cycles per conversion
SHAL_Result multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8);
private:
SHAL_ADC() = default;
ADC_Key m_ADCKey = ADC_Key::INVALID;
//Checks to see if instance is initialized with a proper ADC peripheral tag
bool isValid();
//Enabled peripheral
SHAL_Result enable();
//Disables peripheral
SHAL_Result disable();
SHAL_Result startConversion();
/// Adds an ADC channel to the conversion sequence
/// \param channel Channel to add
/// \param index Index to add channel to (ADC channel will be the nth channel to convert
/// \return Result
SHAL_Result addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t index);
/// Sets the amount of ADC channels to convert
/// \param amount Number of channels to convert
/// \return
SHAL_Result setADCSequenceAmount(uint32_t amount);
};
#define SHAL_ADC(x) ADCManager::getByIndex(x-1)
class ADCManager{
public:
static SHAL_ADC& get(ADC_Key key);
static SHAL_ADC& getByIndex(int index);
ADCManager() = delete;
private:
inline static SHAL_ADC m_ADCs[static_cast<uint8_t>(ADC_Key::NUM_ADC)] = {};
};
#endif //SHMINGO_HAL_SHAL_ADC_H

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@@ -0,0 +1,95 @@
//
// Created by Luca on 9/21/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_REG_H
#define SHMINGO_HAL_SHAL_ADC_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_ADC_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_ADC_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_ADC_REG_H

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@@ -0,0 +1,108 @@
//
// Created by Luca on 9/21/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_TYPES_H
#define SHMINGO_HAL_SHAL_ADC_TYPES_H
//Common register among all ADC peripherals
struct SHAL_ADC_Common_Control_Reg {
volatile uint32_t* reg;
uint32_t VoltageRefEnable;
uint32_t TempSensorEnable;
uint32_t VBatteryEnable;
};
//Register controlling the ADC peripheral clock
struct SHAL_ADC_RCC_Enable_Reg {
volatile uint32_t* reg;
uint32_t mask;
};
//Register with ADC controls
struct SHAL_ADC_Control_Reg {
volatile uint32_t* reg;
uint32_t enable_mask;
uint32_t disable_mask;
uint32_t calibration_mask;
uint32_t start_mask;
};
//Register controlling ADC configuration
struct SHAL_ADC_Config_Reg {
volatile uint32_t* reg;
uint32_t continue_mask;
uint32_t resolution_offset;
uint32_t alignment_offset;
};
//Register for all ADC data
struct SHAL_ADC_Data_Reg {
volatile uint32_t* reg;
uint32_t mask;
};
//Register for the interrupt service routine for ADCs
struct SHAL_ADC_ISR_Reg {
volatile uint32_t* reg;
uint32_t end_of_conversion_mask;
uint32_t end_of_sequence_mask;
uint32_t ready_mask;
};
//Register controlling the clock source for the ADC
struct SHAL_ADC_Clock_Reg {
volatile uint32_t* reg;
uint32_t clear;
uint32_t mask;
};
//Register controlling the sampling time of ADC samples
struct SHAL_ADC_Channel_Sampling_Time_Reg {
volatile uint32_t* reg;
uint32_t channel_offset;
};
//Register controlling the number of conversions to do in one sequence
struct SHAL_ADC_Sequence_Amount_Reg {
volatile uint32_t* reg;
uint32_t offset;
};
/*Register group controlling which ADC channels to convert. DO NOT USE THE FOLLOWING ILLEGAL COMBINATIONS:
*reg 1 + offset 1
*Any sections after the last one (for example, max for a 16 channel register is reg 4 offset 2*/
struct SHAL_ADC_Sequence_Reg {
volatile uint32_t* regs[6];
uint32_t offsets[5];
};
enum class SHAL_ADC_SampleTime : uint32_t {
C1 = 0x00, //1.5 cycles per sample (F0 only, timings change on other ADC architectures)
C2 = 0x01, //7.5 cycles
C3 = 0x02, //13.5 cycles
C4 = 0x03, //28.5 cycles
C5 = 0x04, //41.5 cycles
C6 = 0x05, //55.5 cycles
C7 = 0x06, //71.5 cycles
C8 = 0x07 //239.5 cycles
};
enum class SHAL_ADC_Resolution : uint8_t {
B12 = 0x00,
B10 = 0x01,
B8 = 0x02,
B6 = 0x03,
};
enum class SHAL_ADC_Alignment : uint8_t {
RIGHT = 0x00,
LEFT = 0x01,
};
#endif //SHMINGO_HAL_SHAL_ADC_TYPES_H

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@@ -0,0 +1,12 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_EXTI_REG_F072XB_H
#define SHMINGO_HAL_SHAL_EXTI_REG_F072XB_H
#include "SHAL_CORE.h"
#define EXTI_PENDING_REG(line) (EXTI->PR)
#endif //SHMINGO_HAL_SHAL_EXTI_REG_F072XB_H

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@@ -0,0 +1,28 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H
#define SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H
#include "SHAL_CORE.h"
#include "SHAL_EXTI_TYPES.h"
#define EXTI_PENDING_REG(line) ((line) < 32 ? EXTI->PR1 : EXTI->PR2)
static inline SHAL_EXTI_Interrupt_Mask_Register getEXTIInterruptMaskRegister(uint32_t line){
auto imr = line < 32 ? EXTI->IMR1 : EXTI->IMR2;
return {&imr};
}
static inline SHAL_EXTI_Rising_Trigger_Selection_Register getEXTIRisingTriggerSelectionRegister(uint32_t line){
auto reg = line < 32 ? EXTI->RTSR1 : EXTI->RTSR2;
return {&reg};
}
static inline SHAL_EXTI_Falling_Trigger_Selection_Register getEXTIFallingTriggerSelectionRegister(uint32_t line){
auto reg = line < 32 ? EXTI->FTSR1 : EXTI->FTSR2;
return {&reg};
}
#endif //SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H

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@@ -11,11 +11,12 @@
#include "SHAL_CORE.h"
#include "SHAL_GPIO_REG.h"
#include "SHAL_EXTI_REG.h"
#define DEFINE_EXTI_IRQ(EXTI_Channel) \
extern "C" void EXTI##EXTI_Channel##_IRQHandler(void) { \
if (EXTI->PR & (1 << EXTI_Channel)) { \
EXTI->PR |= (1 << EXTI_Channel); /*clear flag */ \
if (EXTI_PENDING_REG(EXTI_Channel) & (1 << EXTI_Channel)) { \
EXTI_PENDING_REG(EXTI_Channel) |= (1 << EXTI_Channel); /*clear flag */ \
auto cb = EXTI_callbacks[EXTI_Channel]; \
if (cb) cb(); \
}; \
@@ -24,8 +25,8 @@ extern "C" void EXTI##EXTI_Channel##_IRQHandler(void) { \
#define DEFINE_MULTI_EXTI_IRQ(EXTI_Channel_Min, EXTI_Channel_Max) \
extern "C" void EXTI##EXTI_Channel_Min##_##EXTI_Channel_Max##_IRQHandler(void) { \
for(uint8_t line = EXTI_Channel_Min; line <= EXTI_Channel_Max; line++){ \
if (EXTI->PR & (1 << line)) { \
EXTI->PR |= (1 << line); /*clear flag */ \
if (EXTI_PENDING_REG(EXTI_Channel_Max) & (1 << line)) { \
EXTI_PENDING_REG(EXTI_Channel_Max) |= (1 << line); /*clear flag */ \
auto cb = EXTI_callbacks[line]; \
if (cb) cb(); \
}; \

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@@ -0,0 +1,100 @@
//
// Created by Luca on 9/6/2025.
//
#ifndef SHAL_EXTI_REG_H
#define SHAL_EXTI_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_EXTI_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_EXTI_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHAL_EXTI_REG_H

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@@ -0,0 +1,22 @@
//
// Created by Luca on 10/17/2025.
//
#ifndef SHMINGO_HAL_SHAL_EXTI_TYPES_H
#define SHMINGO_HAL_SHAL_EXTI_TYPES_H
#include "SHAL_CORE.h"
struct SHAL_EXTI_Interrupt_Mask_Register {
volatile uint32_t* reg;
};
struct SHAL_EXTI_Rising_Trigger_Selection_Register {
volatile uint32_t* reg;
};
struct SHAL_EXTI_Falling_Trigger_Selection_Register {
volatile uint32_t* reg;
};
#endif //SHMINGO_HAL_SHAL_EXTI_TYPES_H

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@@ -1,47 +0,0 @@
//
// Created by Luca on 9/6/2025.
//
#ifndef SHAL_GPIO_REG_H
#define SHAL_GPIO_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_GPIO_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_GPIO_REG_H

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@@ -20,7 +20,7 @@
X(C0) X(C1) X(C2) X(C3) X(C4) X(C5) X(C6) X(C7) X(C8) X(C9) X(C10) X(C11) X(C12) X(C13) X(C14) X(C15)
//Build enum map of available GPIO pins
//Build enum map of available SHAL_GPIO pins
enum class GPIO_Key : uint8_t {
#define X(key) key,
AVAILABLE_GPIO
@@ -89,7 +89,7 @@ constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
__builtin_unreachable();
}
constexpr SHAL_EXTIO_Register getGPIOEXTICR(const GPIO_Key g){
constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PA,EXTI0_1_IRQn};
case GPIO_Key::A1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PA,EXTI0_1_IRQn};
@@ -143,7 +143,7 @@ constexpr SHAL_EXTIO_Register getGPIOEXTICR(const GPIO_Key g){
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_EXTIO_Register(nullptr,0, EXTI4_15_IRQn); //Unreachable
return SHAL_GPIO_EXTI_Register(nullptr, 0, EXTI4_15_IRQn); //Unreachable
}
__builtin_unreachable();
}
@@ -270,6 +270,79 @@ constexpr uint32_t getGPIOPortNumber(const GPIO_Key g){
__builtin_unreachable();
}
constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
switch(key){
case GPIO_Key::A0:
case GPIO_Key::B0:
case GPIO_Key::C0:
return {0, SHAL_ADC_Channel::CH0};
case GPIO_Key::A1:
case GPIO_Key::B1:
case GPIO_Key::C1:
return {1, SHAL_ADC_Channel::CH1};
case GPIO_Key::A2:
case GPIO_Key::B2:
case GPIO_Key::C2:
return {2, SHAL_ADC_Channel::CH2};
case GPIO_Key::A3:
case GPIO_Key::B3:
case GPIO_Key::C3:
return {3, SHAL_ADC_Channel::CH3};
case GPIO_Key::A4:
case GPIO_Key::B4:
case GPIO_Key::C4:
return {4, SHAL_ADC_Channel::CH4};
case GPIO_Key::A5:
case GPIO_Key::B5:
case GPIO_Key::C5:
return {5, SHAL_ADC_Channel::CH5};
case GPIO_Key::A6:
case GPIO_Key::B6:
case GPIO_Key::C6:
return {6, SHAL_ADC_Channel::CH6};
case GPIO_Key::A7:
case GPIO_Key::B7:
case GPIO_Key::C7:
return {7, SHAL_ADC_Channel::CH7};
case GPIO_Key::A8:
case GPIO_Key::B8:
case GPIO_Key::C8:
return {8, SHAL_ADC_Channel::CH8};
case GPIO_Key::A9:
case GPIO_Key::B9:
case GPIO_Key::C9:
return {9, SHAL_ADC_Channel::CH9};
case GPIO_Key::A10:
case GPIO_Key::B10:
case GPIO_Key::C10:
return {10, SHAL_ADC_Channel::CH10};
case GPIO_Key::A11:
case GPIO_Key::B11:
case GPIO_Key::C11:
return {11, SHAL_ADC_Channel::CH11};
case GPIO_Key::A12:
case GPIO_Key::B12:
case GPIO_Key::C12:
return {12, SHAL_ADC_Channel::CH12};
case GPIO_Key::A13:
case GPIO_Key::B13:
case GPIO_Key::C13:
return {13, SHAL_ADC_Channel::CH13};
case GPIO_Key::A14:
case GPIO_Key::B14:
case GPIO_Key::C14:
return {14, SHAL_ADC_Channel::CH14};
case GPIO_Key::A15:
case GPIO_Key::B15:
case GPIO_Key::C15:
return {15, SHAL_ADC_Channel::CH15};
case GPIO_Key::NUM_GPIO:
case GPIO_Key::INVALID:
return {0, SHAL_ADC_Channel::CH0};
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H

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@@ -0,0 +1,216 @@
//
// Created by Luca on 8/29/2025.
//
#ifndef SHAL_GPIO_REG_F072XB_H
#define SHAL_GPIO_REG_F072XB_H
#include <stm32l432xx.h>
#include <cassert>
#include "SHAL_GPIO_TYPES.h"
#define AVAILABLE_PORTS 3
#define PINS_PER_PORT 16
#define NUM_EXTI_LINES 16
#define AVAILABLE_GPIO \
X(A0) X(A1) X(A2) X(A3) X(A4) X(A5) X(A6) X(A7) X(A8) X(A9) X(A10) X(A11) X(A12) X(A13) X(A14) X(A15) \
X(B0) X(B1) X(B3) X(B4) X(B5) X(B6) X(B7)
//Build enum map of available SHAL_GPIO pins
enum class GPIO_Key : uint8_t {
#define X(key) key,
AVAILABLE_GPIO
#undef X
NUM_GPIO,
INVALID
};
constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {GPIOA,0};
case GPIO_Key::A1: return {GPIOA,1};
case GPIO_Key::A2: return {GPIOA,2};
case GPIO_Key::A3: return {GPIOA,3};
case GPIO_Key::A4: return {GPIOA,4};
case GPIO_Key::A5: return {GPIOA,5};
case GPIO_Key::A6: return {GPIOA,6};
case GPIO_Key::A7: return {GPIOA,7};
case GPIO_Key::A8: return {GPIOA,8};
case GPIO_Key::A9: return {GPIOA,9};
case GPIO_Key::A10: return {GPIOA,10};
case GPIO_Key::A11: return {GPIOA,11};
case GPIO_Key::A12: return {GPIOA,12};
case GPIO_Key::A13: return {GPIOA,13};
case GPIO_Key::A14: return {GPIOA,14};
case GPIO_Key::A15: return {GPIOA,15};
case GPIO_Key::B0: return {GPIOB,0};
case GPIO_Key::B1: return {GPIOB,1};
case GPIO_Key::B3: return {GPIOB,3};
case GPIO_Key::B4: return {GPIOB,4};
case GPIO_Key::B5: return {GPIOB,5};
case GPIO_Key::B6: return {GPIOB,6};
case GPIO_Key::B7: return {GPIOB,7};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_GPIO_Peripheral(nullptr,0); //Unreachable
}
__builtin_unreachable();
}
constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PA,EXTI0_IRQn};
case GPIO_Key::A1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PA,EXTI1_IRQn};
case GPIO_Key::A2: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI2_PA,EXTI2_IRQn};
case GPIO_Key::A3: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI3_PA,EXTI3_IRQn};
case GPIO_Key::A4: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI4_PA,EXTI4_IRQn};
case GPIO_Key::A5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PA,EXTI9_5_IRQn};
case GPIO_Key::A6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PA,EXTI9_5_IRQn};
case GPIO_Key::A7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PA,EXTI9_5_IRQn};
case GPIO_Key::A8: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI8_PA,EXTI9_5_IRQn};
case GPIO_Key::A9: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI9_PA,EXTI9_5_IRQn};
case GPIO_Key::A10: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI10_PA,EXTI15_10_IRQn};
case GPIO_Key::A11: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI11_PA,EXTI15_10_IRQn};
case GPIO_Key::A12: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI12_PA,EXTI15_10_IRQn};
case GPIO_Key::A13: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI13_PA,EXTI15_10_IRQn};
case GPIO_Key::A14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PA,EXTI15_10_IRQn};
case GPIO_Key::A15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PA,EXTI15_10_IRQn};
case GPIO_Key::B0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PB,EXTI0_IRQn};
case GPIO_Key::B1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PB,EXTI1_IRQn};
case GPIO_Key::B3: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI3_PB,EXTI3_IRQn};
case GPIO_Key::B4: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI4_PB,EXTI4_IRQn};
case GPIO_Key::B5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PB,EXTI9_5_IRQn};
case GPIO_Key::B6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PB,EXTI9_5_IRQn};
case GPIO_Key::B7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PB,EXTI9_5_IRQn};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_GPIO_EXTI_Register(nullptr, 0, static_cast<IRQn_Type>(0)); //Unreachable
}
__builtin_unreachable();
}
constexpr SHAL_Peripheral_Register getGPIORCCEnable(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN_Pos};
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN_Pos};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_Peripheral_Register(nullptr,0); //Unreachable
}
__builtin_unreachable();
}
constexpr uint32_t getGPIOPortNumber(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return 0;
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return 0;
}
__builtin_unreachable();
}
constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
switch(key){
case GPIO_Key::A0:
case GPIO_Key::B0:
return {0, SHAL_ADC_Channel::CH0};
case GPIO_Key::A1:
case GPIO_Key::B1:
return {1, SHAL_ADC_Channel::CH1};
case GPIO_Key::A2:
return {2, SHAL_ADC_Channel::CH2};
case GPIO_Key::A3:
case GPIO_Key::B3:
return {3, SHAL_ADC_Channel::CH3};
case GPIO_Key::A4:
case GPIO_Key::B4:
return {4, SHAL_ADC_Channel::CH4};
case GPIO_Key::A5:
case GPIO_Key::B5:
return {5, SHAL_ADC_Channel::CH5};
case GPIO_Key::A6:
case GPIO_Key::B6:
return {6, SHAL_ADC_Channel::CH6};
case GPIO_Key::A7:
case GPIO_Key::B7:
return {7, SHAL_ADC_Channel::CH7};
case GPIO_Key::A8:
return {8, SHAL_ADC_Channel::CH8};
case GPIO_Key::A9:
return {9, SHAL_ADC_Channel::CH9};
case GPIO_Key::A10:
return {10, SHAL_ADC_Channel::CH10};
case GPIO_Key::A11:
return {11, SHAL_ADC_Channel::CH11};
case GPIO_Key::A12:
return {12, SHAL_ADC_Channel::CH12};
case GPIO_Key::A13:
return {13, SHAL_ADC_Channel::CH13};
case GPIO_Key::A14:
return {14, SHAL_ADC_Channel::CH14};
case GPIO_Key::A15:
return {15, SHAL_ADC_Channel::CH15};
case GPIO_Key::NUM_GPIO:
case GPIO_Key::INVALID:
return {0, SHAL_ADC_Channel::CH0};
}
__builtin_unreachable();
}
#endif //SHAL_GPIO_REG_F072XB_H

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@@ -1,29 +0,0 @@
//
// Created by Luca on 9/6/2025.
//
#ifndef SHAL_GPIO_TYPES_H
#define SHAL_GPIO_TYPES_H
#include "SHAL_CORE.h"
struct SHAL_EXTIO_Register{
volatile uint32_t* EXT_ICR;
uint32_t mask;
IRQn_Type IRQN;
};
struct SHAL_GPIO_Peripheral {
GPIO_TypeDef * reg;
unsigned long global_offset;
};
struct SHAL_Peripheral_Register {
volatile uint32_t* reg;
unsigned long offset;
};
#endif //SHMINGO_HAL_SHAL_GPIO_TYPES_H

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@@ -10,26 +10,11 @@
#include <cassert>
#include "SHAL_EXTI_CALLBACK.h"
#include "SHAL_ADC.h"
enum class PinMode : uint8_t{
INPUT_MODE,
OUTPUT_MODE,
ALTERNATE_FUNCTION_MODE,
ANALOG_MODE,
INVALID
};
unsigned long getPinMode(PinMode mode);
enum class TriggerMode : uint8_t{
RISING_EDGE,
FALLING_EDGE,
RISING_FALLING_EDGE
};
//Abstraction of GPIO registers
class GPIO{
//Abstraction of SHAL_GPIO registers
class SHAL_GPIO{
public:
@@ -39,37 +24,67 @@ public:
void setHigh();
void setLow();
/// Uses the ADC to read an analog voltage value
/// \param sampleTime The amount of clock cycles to use for the ADC
/// \return ADC result
uint16_t analogRead(SHAL_ADC_SampleTime sampleTime = SHAL_ADC_SampleTime::C8);
void setPinMode(PinMode mode) volatile;
void setAlternateFunction(GPIO_Alternate_Function AF) volatile;
void setPinType(PinType type) volatile;
void setOutputSpeed(OutputSpeed speed) volatile;
void setInternalResistor(InternalResistorType type) volatile;
void useAsExternalInterrupt(TriggerMode mode, EXTICallback callback);
private:
friend class GPIOManager;
explicit GPIO(GPIO_Key key, PinMode pinMode);
GPIO();
explicit SHAL_GPIO(GPIO_Key key);
SHAL_GPIO();
GPIO_Key m_GPIO_KEY = GPIO_Key::INVALID;
};
//Init GPIO for normal use
#define initGPIO(GPIO_KEY, PIN_MODE) GPIOManager::get(GPIO_KEY, PIN_MODE)
//Init GPIO for use as an external interrupt
#define useGPIOAsInterrupt(GPIO_KEY, Trigger_Mode, Callback) GPIOManager::getInterruptGPIO(GPIO_KEY, Trigger_Mode, Callback)
//Manages instances of GPIO objects
//Init SHAL_GPIO for normal use
#define PIN_TO_KEY(name) GPIO_Key::name
#define PIN(name) GPIOManager::get(PIN_TO_KEY(name))
#define GET_GPIO(key) GPIOManager::get(key)
#define SET_ANALOGREAD_ADC(x) GPIOManager::setGPIOADC(x)
//Manages instances of SHAL_GPIO objects
class GPIOManager{
public:
static GPIO& get(GPIO_Key, PinMode pinMode);
static SHAL_GPIO& get(GPIO_Key);
static void getInterruptGPIO(GPIO_Key key, TriggerMode mode, EXTICallback callback);
static SHAL_ADC getGPIOADC(){ return m_GPIO_ADC;}
static void setGPIOADC(SHAL_ADC adc){m_GPIO_ADC = adc;}
GPIOManager() = delete;
private:
inline static GPIO m_gpios[AVAILABLE_PORTS][PINS_PER_PORT] = {{}};
inline static SHAL_GPIO m_gpios[AVAILABLE_PORTS][PINS_PER_PORT] = {{}};
inline static SHAL_ADC m_GPIO_ADC = SHAL_ADC(1);
};

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@@ -0,0 +1,100 @@
//
// Created by Luca on 9/6/2025.
//
#ifndef SHAL_GPIO_REG_H
#define SHAL_GPIO_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_GPIO_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_GPIO_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_GPIO_REG_H

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@@ -0,0 +1,77 @@
//
// Created by Luca on 9/6/2025.
//
#ifndef SHAL_GPIO_TYPES_H
#define SHAL_GPIO_TYPES_H
#include "SHAL_CORE.h"
#include "SHAL_ADC.h"
#include "SHAL_ADC_TYPES.h"
struct SHAL_GPIO_EXTI_Register{
volatile uint32_t* EXT_ICR; //4 32 bit registers which say which GPIO a line is connected to
uint32_t mask; //Mask for enabling GPIO connection
IRQn_Type IRQN; //IRQ number for enabling lines
};
struct SHAL_GPIO_Peripheral {
GPIO_TypeDef * reg;
unsigned long global_offset;
};
struct SHAL_Peripheral_Register {
volatile uint32_t* reg;
unsigned long offset;
};
struct SHAL_GPIO_Port_Info{
uint8_t number;
SHAL_ADC_Channel ADCChannel;
};
enum class PinMode : uint8_t{
INPUT_MODE = 0x00,
OUTPUT_MODE = 0x01,
ALTERNATE_FUNCTION_MODE = 0x02,
ANALOG_MODE = 0x03,
INVALID = 0x00,
};
enum class GPIO_Alternate_Function : uint8_t{
AF0 = 0x00,
AF1 = 0x01,
AF2 = 0x02,
AF3 = 0x03,
AF4 = 0x04,
AF5 = 0x05,
AF6 = 0x06,
AF7 = 0x07,
};
enum class PinType : uint8_t{
PUSH_PULL = 0x00,
OPEN_DRAIN = 0x01,
};
enum class InternalResistorType : uint8_t{
NO_PULL = 0x00,
PULLUP = 0x01,
PULLDOWN = 0x02,
};
enum class OutputSpeed : uint8_t{
LOW_SPEED = 0x00,
MEDIUM_SPEED = 0x01,
HIGH_SPEED = 0x02,
VERY_HIGH_SPEED = 0x03,
};
enum class TriggerMode : uint8_t{
RISING_EDGE,
FALLING_EDGE,
RISING_FALLING_EDGE
};
#endif //SHMINGO_HAL_SHAL_GPIO_TYPES_H

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@@ -0,0 +1,94 @@
//
// Created by Luca on 9/9/2025.
//
#ifndef SHAL_I2C_REG_F072XB_H
#define SHAL_I2C_REG_F072XB_H
#include "SHAL_CORE.h"
#include <cassert>
#include "SHAL_I2C_TYPES.h"
#define NUM_I2C_BUSES 2
#define SHAL_I2C1 I2C(1)
#define SHAL_I2C2 I2C(2)
enum class I2C_Pair : uint8_t{
//I2C_1
SCL1B6_SDA1B7, //AF1
SCL1B8_SDA1B9, //AF1
//I2C_2
SCL2B10_SDA2B11, //AF1
SCL2B13_SDA2B14, //AF5
NUM_PAIRS,
INVALID
};
constexpr SHAL_I2C_Pair getI2CPair(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1B6_SDA1B7: return {I2C1,GPIO_Key::B6,GPIO_Key::B7,GPIO_Alternate_Function::AF1,GPIO_Alternate_Function::AF1};
case I2C_Pair::SCL1B8_SDA1B9: return {I2C1,GPIO_Key::B8,GPIO_Key::B9,GPIO_Alternate_Function::AF1,GPIO_Alternate_Function::AF1};
case I2C_Pair::SCL2B10_SDA2B11: return {I2C2,GPIO_Key::B10,GPIO_Key::B11,GPIO_Alternate_Function::AF1,GPIO_Alternate_Function::AF1};
case I2C_Pair::SCL2B13_SDA2B14: return {I2C2,GPIO_Key::B13,GPIO_Key::B14,GPIO_Alternate_Function::AF5,GPIO_Alternate_Function::AF5};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
return {nullptr,GPIO_Key::INVALID,GPIO_Key::INVALID,GPIO_Alternate_Function::AF0,GPIO_Alternate_Function::AF0};
}
__builtin_unreachable();
}
constexpr SHAL_I2C_Enable_Reg getI2CEnableReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1B6_SDA1B7:
case I2C_Pair::SCL1B8_SDA1B9:
return {&RCC->APB1ENR,RCC_APB1ENR_I2C1EN};
case I2C_Pair::SCL2B10_SDA2B11:
case I2C_Pair::SCL2B13_SDA2B14:
return {&RCC->APB1ENR,RCC_APB1ENR_I2C2EN};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
constexpr SHAL_I2C_Reset_Reg getI2CResetReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1B6_SDA1B7:
case I2C_Pair::SCL1B8_SDA1B9:
return {&RCC->APB1RSTR,RCC_APB1RSTR_I2C1RST};
case I2C_Pair::SCL2B10_SDA2B11:
case I2C_Pair::SCL2B13_SDA2B14:
return {&RCC->APB1RSTR,RCC_APB1RSTR_I2C2RST};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
//Gets all the bits in the I2C timer register, these values should rarely be manually set, but I wanted to support it anyway
constexpr SHAL_I2C_Timing_Reg getI2CTimerReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1B6_SDA1B7:
case I2C_Pair::SCL1B8_SDA1B9:
return {&I2C1->TIMINGR,31,23,19,15,7};
case I2C_Pair::SCL2B10_SDA2B11:
case I2C_Pair::SCL2B13_SDA2B14:
return {&I2C2->TIMINGR,31,23,19,15,7};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
__builtin_unreachable();
}
__builtin_unreachable();
}
#endif //SHAL_I2C_REG_F072XB_H

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@@ -0,0 +1,83 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_I2C_REG_L432KC_H
#define SHMINGO_HAL_SHAL_I2C_REG_L432KC_H
#include "SHAL_CORE.h"
#include "SHAL_I2C_TYPES.h"
#define NUM_I2C_BUSES 3
enum class I2C_Pair : uint8_t{
//I2C_1
SCL1A9_SDA1A10, //AF4
SCL1B6_SDA1B7, //AF4
//I2C_3
SCL3A7_SDA3B4, //AF4
NUM_PAIRS,
INVALID
};
constexpr SHAL_I2C_Pair getI2CPair(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10: return {I2C1,GPIO_Key::A9,GPIO_Key::A10,GPIO_Alternate_Function::AF4,GPIO_Alternate_Function::AF4};
case I2C_Pair::SCL1B6_SDA1B7: return {I2C1,GPIO_Key::B6,GPIO_Key::B7,GPIO_Alternate_Function::AF4,GPIO_Alternate_Function::AF4};
case I2C_Pair::SCL3A7_SDA3B4: return {I2C3,GPIO_Key::A7,GPIO_Key::B4,GPIO_Alternate_Function::AF4,GPIO_Alternate_Function::AF4};
case I2C_Pair::INVALID:
assert(false);
return {nullptr,GPIO_Key::INVALID,GPIO_Key::INVALID,GPIO_Alternate_Function::AF0,GPIO_Alternate_Function::AF0};
}
__builtin_unreachable();
}
constexpr SHAL_I2C_Enable_Reg getI2CEnableReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10:
case I2C_Pair::SCL1B6_SDA1B7:
return {&RCC->APB1ENR1,RCC_APB1ENR1_I2C1EN};
case I2C_Pair::SCL3A7_SDA3B4:
return {&RCC->APB1ENR1,RCC_APB1ENR1_I2C3EN};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
constexpr SHAL_I2C_Reset_Reg getI2CResetReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10:
case I2C_Pair::SCL1B6_SDA1B7:
return {&RCC->APB1RSTR1,RCC_APB1RSTR1_I2C1RST};
case I2C_Pair::SCL3A7_SDA3B4:
return {&RCC->APB1RSTR1,RCC_APB1RSTR1_I2C3RST};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
//Gets all the bits in the I2C timer register, these values should rarely be manually set, but I wanted to support it anyway
constexpr SHAL_I2C_Timing_Reg getI2CTimerReg(const I2C_Pair pair){
switch(pair){
case I2C_Pair::SCL1A9_SDA1A10:
case I2C_Pair::SCL1B6_SDA1B7:
return {&I2C1->TIMINGR,31,23,19,15,7};
case I2C_Pair::SCL3A7_SDA3B4:
return {&I2C3->TIMINGR,31,23,19,15,7};
case I2C_Pair::NUM_PAIRS:
case I2C_Pair::INVALID:
assert(false);
__builtin_unreachable();
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_I2C_REG_L432KC_H

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@@ -0,0 +1,75 @@
//
// Created by Luca on 9/9/2025.
//
#ifndef SHMINGO_HAL_SHAL_I2C_H
#define SHMINGO_HAL_SHAL_I2C_H
#include <cstdio>
#include "SHAL_CORE.h"
#include "SHAL_I2C_REG.h"
class SHAL_I2C{
friend class I2CManager;
public:
void init(I2C_Pair pair) volatile;
/// General I2C function to send commands to a device, then read back any returned data if necessary
/// \param addr address of slave device
/// \param writeData pointer to array of write commands
/// \param writeLen number of write commands
/// \param readData pointer to buffer to write received data to
/// \param readLen number of bytes to be read
void masterWriteRead(uint8_t addr,const uint8_t* writeData, size_t writeLen, uint8_t* readData, size_t readLen);
uint8_t masterWriteReadByte(uint8_t addr, const uint8_t* writeData, size_t writeLen);
/// Function to write an array of commands to an I2C device
/// \param addr Address of slave device
/// \param writeData Pointer to array of commands
/// \param writeLen Number of commands
void masterWrite(uint8_t addr, const uint8_t* writeData, uint8_t writeLen);
/// Function to read bytes from an I2C device
/// \param addr Address of slave device
/// \param readBuffer Pointer to buffer where data will be placed
/// \param bytesToRead Number of bytes to read
void masterRead(uint8_t addr, uint8_t* readBuffer, uint8_t bytesToRead);
//Manually set the clock configuration. Refer to your MCU's reference manual for examples
void setClockConfig(uint8_t prescaler, uint8_t dataSetupTime, uint8_t dataHoldTime, uint8_t SCLHighPeriod, uint8_t SCLLowPeriod);
//Set clock configuration based on a value calculated from STM32CubeMX, or other similar tools
void setClockConfig(uint32_t configuration);
private:
SHAL_I2C() = default;
I2C_Pair m_I2CPair = I2C_Pair::INVALID; //Initialize to invalid
};
#define I2C(num) I2CManager::get(num)
class I2CManager{
public:
static SHAL_I2C& get(uint8_t i2c);
I2CManager() = delete;
private:
inline static SHAL_I2C m_I2CBuses[NUM_I2C_BUSES] = {};
};
#endif //SHMINGO_HAL_SHAL_I2C_H

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@@ -0,0 +1,93 @@
//
// Created by Luca on 9/9/2025.
//
#ifndef SHAL_I2C_REG_H
#define SHAL_I2C_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_I2C_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_I2C_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32 device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHAL_I2C_REG_H

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@@ -0,0 +1,40 @@
//
// Created by Luca on 9/9/2025.
//
#ifndef SHMINGO_HAL_SHAL_I2C_TYPES_H
#define SHMINGO_HAL_SHAL_I2C_TYPES_H
#include "SHAL_CORE.h"
#include "SHAL_GPIO_REG.h"
//Information necessary for I2C
struct SHAL_I2C_Pair {
I2C_TypeDef* I2CReg;
GPIO_Key SCL_Key;
GPIO_Key SDA_Key;
GPIO_Alternate_Function SCL_Mask;
GPIO_Alternate_Function SDA_Mask;
};
struct SHAL_I2C_Enable_Reg{
volatile uint32_t* reg;
uint32_t mask;
};
struct SHAL_I2C_Reset_Reg{
volatile uint32_t* reg;
uint32_t mask;
};
//Manual values for I2C timer register
struct SHAL_I2C_Timing_Reg{
volatile uint32_t* reg;
uint8_t prescaler_offset;
uint8_t dataSetupTime_offset;
uint8_t dataHoldTime_offset;
uint8_t SCLHighPeriod_offset;
uint8_t SCLLowPeriod_offset;
};
#endif //SHMINGO_HAL_SHAL_I2C_TYPES_H

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@@ -1,44 +0,0 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_REG_H
#define SHMINGO_HAL_SHAL_TIM_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_TIM_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_TIM_REG_H

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@@ -6,8 +6,8 @@
******************************************************************************
*/
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#ifndef SHAL_TIM_REG_F072XB_H
#define SHAL_TIM_REG_F072XB_H
#include <cassert>
#include <stm32f072xb.h>
@@ -29,6 +29,17 @@ enum class Timer_Key : uint8_t { //For STM32F072
S_TIM_INVALID
};
#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
#define SHAL_TIM3 TimerManager::get(Timer_Key::S_TIM3)
#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
#define SHAL_TIM14 TimerManager::get(Timer_Key::S_TIM14)
#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
#define SHAL_TIM17 TimerManager::get(Timer_Key::S_TIM17)
//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
constexpr TIM_RCC_Enable getTimerRCC(Timer_Key t) {

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@@ -0,0 +1,140 @@
/**
******************************************************************************
* @file SHAL_TIM_REG.h
* @author Luca Lizaranzu
* @brief Defines universal macros and objects used across all STM32 families
******************************************************************************
*/
#ifndef SHAL_TIM_REG_L432KC_H
#define SHAL_TIM_REG_L432KC_H
#include <cassert>
#include <stm32l432xx.h>
#include "SHAL_CORE.h"
#include "SHAL_TIM_TYPES.h"
enum class Timer_Key : uint8_t { //For STM32L432
S_TIM1,
S_TIM2,
S_TIM6,
S_TIM7,
S_TIM15,
S_TIM16,
NUM_TIMERS,
S_TIM_INVALID
};
//Lookup table for timer typedefs
static volatile TIM_TypeDef* TIM_TABLE[6] = {
TIM1,
TIM2,
TIM6,
TIM7,
TIM15,
TIM16,
};
static IRQn_Type IRQN_TABLE[6] = {
TIM1_TRG_COM_IRQn,
TIM2_IRQn,
TIM6_DAC_IRQn,
TIM7_IRQn,
TIM1_BRK_TIM15_IRQn,
TIM1_UP_TIM16_IRQn
};
#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
static inline SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->SR;
return res;
}
static inline SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk, TIM_CR1_UDIS, TIM_CR1_OPM, TIM_CR1_CMS_Pos};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
static inline SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->DIER;
return res;
}
static inline SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->EGR;
return res;
}
static inline SHAL_TIM_Prescaler_Register getTimerPrescalerRegister(Timer_Key key){
SHAL_TIM_Prescaler_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->PSC;
return res;
}
static inline SHAL_TIM_Auto_Reload_Register getTimerAutoReloadRegister(Timer_Key key){
SHAL_TIM_Auto_Reload_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->ARR;
return res;
}
//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
static inline SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN};
case Timer_Key::S_TIM6: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN};
case Timer_Key::S_TIM7: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
}
__builtin_unreachable();
}
//Get timer IRQN from lookup table
static inline IRQn_Type getTimerIRQn(Timer_Key t) {
return IRQN_TABLE[static_cast<uint8_t>(t)];
}
#endif

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@@ -1,15 +0,0 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_TYPES_H
#define SHMINGO_HAL_SHAL_TIM_TYPES_H
#include "SHAL_CORE.h"
struct TIM_RCC_Enable{
volatile uint32_t* busEnableReg;
uint32_t offset;
};
#endif //SHMINGO_HAL_SHAL_TIM_TYPES_H

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@@ -9,7 +9,7 @@
#ifndef SHAL_TIM_H
#define SHAL_TIM_H
#include "SHAL_TIM_REG_F072xB.h"
#include "SHAL_TIM_REG.h"
#include "SHAL_TIM_CALLBACK.h"
#include <array>
@@ -18,6 +18,11 @@ class Timer {
friend class TimerManager;
public:
/// Initializes a timer
/// \param prescaler The amount of times the base clock has to cycle before the timer adds one to the count
/// \param autoReload The number of timer counts before the count is reset and IRQ is called
void init(uint32_t prescaler, uint32_t autoReload);
//Starts the counter
void start();
@@ -35,7 +40,7 @@ public:
//Set TIMER_KEY IRQ callback function
void setCallbackFunc(TimerCallback callback){
registerTimerCallback(TIMER_KEY, callback);
registerTimerCallback(m_key, callback);
}
private:
@@ -43,18 +48,22 @@ private:
explicit Timer(Timer_Key t);
Timer();
Timer_Key TIMER_KEY;
Timer_Key m_key;
};
#define getTimer(timer_key) TimerManager::get(timer_key)
#define TIM(num) TimerManager::getTimerFromIndex(num)
//Manages all timers so user does not have to personally initialize
class TimerManager{
public:
static Timer& get(Timer_Key);
static Timer& getTimerFromIndex(uint8_t index){return timers[index];}
TimerManager() = delete;
private:

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@@ -13,11 +13,12 @@
#include "SHAL_CORE.h"
#include "SHAL_TIM_REG.h"
#define DEFINE_TIMER_IRQ(key, irq_handler) \
extern "C" void irq_handler(void) { \
auto tim_reg = getTimerRegister(key); \
if (tim_reg->SR & TIM_SR_UIF) { \
tim_reg->SR &= ~TIM_SR_UIF; /* clear flag */ \
auto tim_status_reg = getTimerStatusRegister(key); \
if (*tim_status_reg.reg & tim_status_reg.update_interrupt_flag_mask) { \
SHAL_clear_bitmask(tim_status_reg.reg,tim_status_reg.update_interrupt_flag_mask); /* clear flag */ \
auto cb = timer_callbacks[static_cast<int>(key)]; \
if (cb) cb(); \
}; \

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@@ -0,0 +1,95 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_TIM_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_TIM_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHAL_TIM_REG_H

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@@ -0,0 +1,48 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_TIM_TYPES_H
#define SHAL_TIM_TYPES_H
#include "SHAL_CORE.h"
struct SHAL_TIM_RCC_Register{
volatile uint32_t* reg;
uint32_t enable_mask;
};
struct SHAL_TIM_Control_Register_1 {
volatile uint32_t* reg;
uint32_t counter_enable_mask;
uint32_t update_disable_mask;
uint32_t one_pulse_mode_mask;
uint32_t center_align_mode_offset;
};
struct SHAL_TIM_DMA_Interrupt_Enable_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_enable_mask;
};
struct SHAL_TIM_Status_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_flag_mask;
};
struct SHAL_TIM_Event_Generation_Register {
volatile uint32_t* reg;
uint32_t update_generation_mask;
};
struct SHAL_TIM_Prescaler_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_TIM_Auto_Reload_Register {
volatile uint32_t* reg;
uint32_t offset;
};
#endif //SHMINGO_HAL_SHAL_TIM_TYPES_H

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@@ -1,50 +0,0 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_UART_REG_H
#define SHAL_UART_REG_H
//
// Created by Luca on 9/6/2025.
//
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_UART_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_UART_REG_H

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@@ -12,8 +12,13 @@
#define NUM_USART_LINES 4
#define SHAL_UART1 UART(1)
#define SHAL_UART2 UART(2)
#define SHAL_UART3 UART(3)
#define SHAL_UART4 UART(4)
//Valid usart Tx and Rx pairings for STM32F072
enum class UART_Pair : uint8_t{
enum class UART_Pair_Key : uint8_t{
//UART1
Tx1A9_Rx1A10,
Tx1B6_Rx1B7,
@@ -36,81 +41,81 @@ enum class UART_Pair : uint8_t{
};
constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){
constexpr SHAL_UART_Pair getUARTPair(const UART_Pair_Key pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10: return {USART1,GPIO_Key::A9,GPIO_Key::A10,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx1B6_Rx1B7: return {USART1,GPIO_Key::B6,GPIO_Key::B7,AF_Mask::AF0,AF_Mask::AF0};
case UART_Pair::Tx2A2_Rx2A3: return {USART2,GPIO_Key::A2,GPIO_Key::A3,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx2A14_Rx2A15: return {USART2,GPIO_Key::A14,GPIO_Key::A15,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx3B10_Rx3B11: return {USART3,GPIO_Key::B10,GPIO_Key::B11,AF_Mask::AF4,AF_Mask::AF4};
case UART_Pair::Tx3C4_Rx3C5: return {USART3,GPIO_Key::C4,GPIO_Key::C5,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx3C10_Rx3C11: return {USART3,GPIO_Key::C10,GPIO_Key::C11,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx4A0_Rx4A1: return {USART4,GPIO_Key::A0,GPIO_Key::A1,AF_Mask::AF4,AF_Mask::AF4};
case UART_Pair::Tx4C10_Rx4C11: return {USART4,GPIO_Key::C10,GPIO_Key::C11,AF_Mask::AF0,AF_Mask::AF0};
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
case UART_Pair_Key::Tx1A9_Rx1A10: return {USART1, GPIO_Key::A9, GPIO_Key::A10, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx1B6_Rx1B7: return {USART1, GPIO_Key::B6, GPIO_Key::B7, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
case UART_Pair_Key::Tx2A2_Rx2A3: return {USART2, GPIO_Key::A2, GPIO_Key::A3, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx2A14_Rx2A15: return {USART2, GPIO_Key::A14, GPIO_Key::A15, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx3B10_Rx3B11: return {USART3, GPIO_Key::B10, GPIO_Key::B11, GPIO_Alternate_Function::AF4, GPIO_Alternate_Function::AF4};
case UART_Pair_Key::Tx3C4_Rx3C5: return {USART3, GPIO_Key::C4, GPIO_Key::C5, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx3C10_Rx3C11: return {USART3, GPIO_Key::C10, GPIO_Key::C11, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx4A0_Rx4A1: return {USART4, GPIO_Key::A0, GPIO_Key::A1, GPIO_Alternate_Function::AF4, GPIO_Alternate_Function::AF4};
case UART_Pair_Key::Tx4C10_Rx4C11: return {USART4, GPIO_Key::C10, GPIO_Key::C11, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr,GPIO_Key::INVALID,GPIO_Key::INVALID,AF_Mask::AF0,AF_Mask::AF0};
return {nullptr, GPIO_Key::INVALID, GPIO_Key::INVALID, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
}
__builtin_unreachable();
}
constexpr uint8_t getUARTChannel(const UART_Pair pair){
constexpr uint8_t getUARTChannel(const UART_Pair_Key pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10:
case UART_Pair::Tx1B6_Rx1B7:
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return 0;
case UART_Pair::Tx2A2_Rx2A3:
case UART_Pair::Tx2A14_Rx2A15:
case UART_Pair_Key::Tx2A2_Rx2A3:
case UART_Pair_Key::Tx2A14_Rx2A15:
return 1;
case UART_Pair::Tx3B10_Rx3B11:
case UART_Pair::Tx3C4_Rx3C5:
case UART_Pair::Tx3C10_Rx3C11:
case UART_Pair_Key::Tx3B10_Rx3B11:
case UART_Pair_Key::Tx3C4_Rx3C5:
case UART_Pair_Key::Tx3C10_Rx3C11:
return 2;
case UART_Pair::Tx4A0_Rx4A1:
case UART_Pair::Tx4C10_Rx4C11:
case UART_Pair_Key::Tx4A0_Rx4A1:
case UART_Pair_Key::Tx4C10_Rx4C11:
return 3;
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return 0;
}
__builtin_unreachable();
}
constexpr SHAL_UART_ENABLE_REG getUARTEnableReg(const UART_Pair pair){
constexpr SHAL_UART_Enable_Register getUARTEnableReg(const UART_Pair_Key pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10:
case UART_Pair::Tx1B6_Rx1B7:
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return {&RCC->APB2ENR,RCC_APB2ENR_USART1EN};
case UART_Pair::Tx2A2_Rx2A3:
case UART_Pair::Tx2A14_Rx2A15:
case UART_Pair_Key::Tx2A2_Rx2A3:
case UART_Pair_Key::Tx2A14_Rx2A15:
return {&RCC->APB1ENR,RCC_APB1ENR_USART2EN};
case UART_Pair::Tx3B10_Rx3B11:
case UART_Pair::Tx3C4_Rx3C5:
case UART_Pair::Tx3C10_Rx3C11:
case UART_Pair_Key::Tx3B10_Rx3B11:
case UART_Pair_Key::Tx3C4_Rx3C5:
case UART_Pair_Key::Tx3C10_Rx3C11:
return {&RCC->APB1ENR,RCC_APB1ENR_USART3EN};
case UART_Pair::Tx4A0_Rx4A1:
case UART_Pair::Tx4C10_Rx4C11:
case UART_Pair_Key::Tx4A0_Rx4A1:
case UART_Pair_Key::Tx4C10_Rx4C11:
return {&RCC->APB1ENR,RCC_APB1ENR_USART4EN};
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
constexpr uint32_t getAFMask(const AF_Mask mask){
constexpr uint32_t getAFMask(const GPIO_Alternate_Function mask){
switch(mask){
case AF_Mask::AF0: return 0x00;
case AF_Mask::AF1: return 0x01;
case AF_Mask::AF2: return 0x02;
case AF_Mask::AF3: return 0x03;
case AF_Mask::AF4: return 0x04;
case AF_Mask::AF5: return 0x05;
case AF_Mask::AF6: return 0x06;
case AF_Mask::AF7: return 0x07;
case GPIO_Alternate_Function::AF0: return 0x00;
case GPIO_Alternate_Function::AF1: return 0x01;
case GPIO_Alternate_Function::AF2: return 0x02;
case GPIO_Alternate_Function::AF3: return 0x03;
case GPIO_Alternate_Function::AF4: return 0x04;
case GPIO_Alternate_Function::AF5: return 0x05;
case GPIO_Alternate_Function::AF6: return 0x06;
case GPIO_Alternate_Function::AF7: return 0x07;
}
__builtin_unreachable();
}

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@@ -0,0 +1,104 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_UART_REG_L432KC_H
#define SHAL_UART_REG_L432KC_H
#include <stm32l432xx.h>
#include <cassert>
#include "SHAL_UART_TYPES.h"
#define NUM_USART_LINES 4
#define SHAL_UART1 UART(1)
#define SHAL_UART2 UART(2)
//Valid usart Tx and Rx pairings for STM32L432KC
enum class UART_Pair_Key : uint8_t{
//UART1
Tx1A9_Rx1A10,
Tx1B6_Rx1B7,
//UART2
Tx2A2_Rx2A3,
NUM_PAIRS,
INVALID
};
static inline SHAL_UART_Pair getUARTPair(const UART_Pair_Key pair){
switch(pair){
case UART_Pair_Key::Tx1A9_Rx1A10: return {USART1, GPIO_Key::A9, GPIO_Key::A10, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::Tx1B6_Rx1B7: return {USART1, GPIO_Key::B6, GPIO_Key::B7, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::Tx2A2_Rx2A3: return {USART2, GPIO_Key::A2, GPIO_Key::A3, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
__builtin_unreachable();
}
__builtin_unreachable();
}
static inline uint8_t getUARTChannel(const UART_Pair_Key pair){ //TODO remove?
switch(pair){
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return 0;
case UART_Pair_Key::Tx2A2_Rx2A3:
return 1;
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return 0;
}
__builtin_unreachable();
}
constexpr SHAL_UART_Enable_Register getUARTEnableReg(const UART_Pair_Key pair){
switch(pair){
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return {&RCC->APB2ENR,RCC_APB2ENR_USART1EN};
case UART_Pair_Key::Tx2A2_Rx2A3:
return {&RCC->APB1ENR1,RCC_APB1ENR1_USART2EN};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
static inline SHAL_UART_Control_Register_1 getUARTControlRegister1(UART_Pair_Key key){
SHAL_UART_Control_Register_1 res = {nullptr, USART_CR1_UE, USART_CR1_TE, USART_CR1_RE};
res.reg = &getUARTPair(key).USARTReg->CR1;
return res;
};
static inline SHAL_UART_Baud_Rate_Generation_Register getUARTBaudRateGenerationRegister(UART_Pair_Key key){
SHAL_UART_Baud_Rate_Generation_Register res = {nullptr, 1UL << 15}; //TODO un-hardcode if other devices have wider baud rate allowances
res.reg = &getUARTPair(key).USARTReg->BRR;
return res;
};
static inline SHAL_UART_Transmit_Data_Register getUARTTransmitDataRegister(UART_Pair_Key key){
SHAL_UART_Transmit_Data_Register res = {nullptr, 1UL << 15}; //TODO un-hardcode if other devices have wider baud rate allowances
res.reg = &getUARTPair(key).USARTReg->TDR;
return res;
};
static inline SHAL_UART_ISR_FIFO_Disabled getUARTISRFifoDisabled(UART_Pair_Key key){
SHAL_UART_ISR_FIFO_Disabled res = {nullptr, USART_ISR_TXE};
res.reg = &getUARTPair(key).USARTReg->ISR;
return res;
};
#endif //SHAL_UART_REG_F072XB_H

View File

@@ -1,37 +0,0 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_UART_TYPES_H
#define SHAL_UART_TYPES_H
#include "SHAL_CORE.h"
#include "SHAL_GPIO_REG.h"
enum class AF_Mask : uint8_t{
AF0,
AF1,
AF2,
AF3,
AF4,
AF5,
AF6,
AF7
};
//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping
struct SHAL_UART_Pair{
USART_TypeDef* USARTReg;
GPIO_Key TxKey;
GPIO_Key RxKey;
AF_Mask TxMask;
AF_Mask RxMask;
};
struct SHAL_UART_ENABLE_REG{
volatile uint32_t* reg;
uint32_t mask;
};
#endif //SHMINGO_HAL_SHAL_UART_TYPES_H

View File

@@ -2,7 +2,7 @@
******************************************************************************
* @file SHAL_TIM.h
* @author Luca Lizaranzu
* @brief Relating to UART and USART object abstractions
* @brief Relating to SHAL_UART and USART object abstractions
******************************************************************************
*/
@@ -10,12 +10,15 @@
#define SHMINGO_HAL_SHAL_UART_H
#include "SHAL_UART_REG.h"
#include "SHAL_UART_TYPES.h"
class UART{
class SHAL_UART{
friend class UARTManager;
public:
void init(UART_Pair_Key pair);
//begins Tx and Usart TODO either modify this function or add a new one that supports Rx
void begin(uint32_t baudRate) volatile;
@@ -27,30 +30,28 @@ public:
private:
UART() = default; //Initializer for array
SHAL_UART() = default; //Initializer for array
//Creates a UART based on a pair of two valid U(S)ART pins
explicit UART(UART_Pair pair);
//Creates a SHAL_UART based on a pair of two valid U(S)ART pins
UART_Pair m_UARTPair = UART_Pair::INVALID;
UART_Pair_Key m_key = UART_Pair_Key::INVALID;
};
#define getUART(uart_pair) UARTManager::get(uart_pair)
#define UART(num) UARTManager::get(num)
class UARTManager{
public:
static UART& get(UART_Pair pair);
static SHAL_UART& get(uint8_t uart);
UARTManager() = delete;
private:
inline static UART m_UARTs[NUM_USART_LINES] = {};
inline static SHAL_UART m_UARTs[NUM_USART_LINES] = {};
};

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@@ -0,0 +1,97 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_UART_REG_H
#define SHAL_UART_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_UART_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "SHAL_UART_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_UART_REG_H

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@@ -0,0 +1,51 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_UART_TYPES_H
#define SHAL_UART_TYPES_H
#include "SHAL_CORE.h"
#include "SHAL_GPIO_REG.h"
//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping
struct SHAL_UART_Pair{
USART_TypeDef* USARTReg;
GPIO_Key TxKey;
GPIO_Key RxKey;
GPIO_Alternate_Function TxAlternateFunctionMask;
GPIO_Alternate_Function RxAlternateFunctionMask;
};
struct SHAL_UART_Enable_Register{
volatile uint32_t* reg;
uint32_t mask;
};
struct SHAL_UART_Control_Register_1 {
volatile uint32_t* reg;
uint32_t usart_enable_mask;
uint32_t transmit_enable_mask;
uint32_t receive_enable_mask;
};
struct SHAL_UART_Baud_Rate_Generation_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_UART_Transmit_Data_Register {
volatile uint16_t* reg;
uint16_t offset;
};
struct SHAL_UART_ISR_FIFO_Disabled {
volatile uint32_t* reg;
uint32_t transmit_data_register_empty_mask;
};
#endif //SHMINGO_HAL_SHAL_UART_TYPES_H

View File

@@ -11,5 +11,8 @@
#include "SHAL_TIM.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART.h"
#include "SHAL_ADC.h"
#endif

View File

@@ -1,118 +0,0 @@
//
// Created by Luca on 8/30/2025.
//
#include "SHAL_GPIO.h"
#include "SHAL_EXTI_CALLBACK.h"
unsigned long getPinMode(PinMode mode){
switch(mode){
case PinMode::INPUT_MODE:
return 0b00;
case PinMode::OUTPUT_MODE:
return 0b01;
case PinMode::ALTERNATE_FUNCTION_MODE:
return 0b10;
case PinMode::ANALOG_MODE:
return 0b11;
case PinMode::INVALID:
assert(false);
return 0;
}
__builtin_unreachable();
}
GPIO::GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
GPIO::GPIO(GPIO_Key key, PinMode pinMode) : m_GPIO_KEY(key) {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(key);
auto gpioRegister = gpioPeripheral.reg;
unsigned long registerOffset = gpioPeripheral.global_offset;
volatile unsigned long* gpioEnable = getGPIORCCEnable(key).reg;
unsigned long gpioOffset = getGPIORCCEnable(key).offset;
*gpioEnable |= (1 << gpioOffset); //Set enable flag
gpioRegister->MODER &= ~(0b11 << (2 * registerOffset)); //Clear any previous mode
gpioRegister->MODER |= (getPinMode(pinMode) << (2 * registerOffset)); //Set mode based on pinmode bit structure
}
void GPIO::setLow() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR &= ~(1 << gpioPeripheral.global_offset);
}
void GPIO::setHigh() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR |= (1 << gpioPeripheral.global_offset);
}
void GPIO::toggle() volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR ^= (1 << gpioPeripheral.global_offset);
}
GPIO& GPIOManager::get(GPIO_Key key, PinMode pinMode) {
unsigned int gpioPort = getGPIOPortNumber(key);
unsigned long gpioPin = getGPIORegister(key).global_offset; //Use existing structs to get offset
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = GPIO(key,pinMode);
}
return m_gpios[gpioPort][gpioPin];
}
void GPIOManager::getInterruptGPIO(GPIO_Key key, TriggerMode triggerMode, EXTICallback callback) {
uint32_t gpioPort = getGPIOPortNumber(key);
uint32_t gpioPin = getGPIORegister(key).global_offset; //Use existing structs to get offset
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = GPIO(key,PinMode::INPUT_MODE); //Hardcode input mode for interrupt
}
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; //Enable EXT, TODO check if this is different across STM32 models
NVIC_EnableIRQ(getGPIOEXTICR(key).IRQN); //Enable IRQN for pin
EXTI->IMR |= (1 << gpioPin); //Enable correct EXTI line
SHAL_EXTIO_Register EXTILineEnable = getGPIOEXTICR(key);
*EXTILineEnable.EXT_ICR |= EXTILineEnable.mask; //Set bits to enable correct port on correct line TODO Find way to clear bits before
uint32_t rising_mask = 0x00;
uint32_t falling_mask = 0x00;
//Set rising and falling edge triggers based on pin offset (enabled EXTI line)
switch(triggerMode){
case TriggerMode::RISING_EDGE:
rising_mask = 1 << gpioPin;
break;
case TriggerMode::FALLING_EDGE:
falling_mask = 1 << gpioPin;
break;
case TriggerMode::RISING_FALLING_EDGE:
falling_mask = 1 << gpioPin;
falling_mask = 1 << gpioPin;
}
//Set triggers
EXTI->RTSR |= rising_mask;
EXTI->FTSR |= falling_mask;
//Set callback
registerEXTICallback(key,callback);
__enable_irq(); //Enable IRQ just in case
}

View File

@@ -1,82 +0,0 @@
/**
******************************************************************************
* @file SHAL_TIM.h
* @author Luca Lizaranzu
* @brief Related to USART and UART abstractions
******************************************************************************
*/
#include "SHAL_UART.h"
#include "SHAL_GPIO.h"
UART::UART(const UART_Pair pair) : m_UARTPair(pair){
SHAL_UART_Pair uart_pair = getUARTPair(pair); //Get the UART_PAIR information to be initialized
//Get the GPIO pins for this UART setup
GPIO_Key Tx_Key = uart_pair.TxKey; //Tx pin
GPIO_Key Rx_Key = uart_pair.RxKey; //Rx pin
uint8_t Tx_Pin = getGPIORegister(Tx_Key).global_offset;
uint8_t Rx_Pin = getGPIORegister(Rx_Key).global_offset;
initGPIO(Tx_Key,PinMode::ALTERNATE_FUNCTION_MODE); //Initialize Tx GPIO with alternate function (initializes GPIO port as well)
initGPIO(Rx_Key,PinMode::ALTERNATE_FUNCTION_MODE); //Initialize Rx GPIO with alternate function
//Determine which AFR register (high or low) to write depending on pin
uint8_t TxAFR = Tx_Pin < 8 ? 0 : 1; //Use AFR[0] if pin < 8, AFR[1] if pin >= 8
uint8_t RxAFR = Rx_Pin < 8 ? 0 : 1;
/*Apply Alternate Function masks to the AFR registers for each GPIO to enable alternate functions
* The AFR register for GPIO_Typedef* is actually two registers - a low reg and high reg.
* The low reg handles pins 0-7, and the high reg handles 8-15.
* Each pin gets 4 bits in the register for AFR0 - AFR7. Hence 8 * 4 = 32 bits.
* Each AFR is a different function, look at the DATASHEET (not reference manual) to find these alternate function mappings
*/
getGPIORegister(Tx_Key).reg->AFR[TxAFR] |= getAFMask(uart_pair.TxMask) << (4 * (Tx_Pin % 8));
getGPIORegister(Rx_Key).reg->AFR[RxAFR] |= getAFMask(uart_pair.RxMask) << (4 * (Rx_Pin % 8));
SHAL_UART_ENABLE_REG pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the UART channel
*pairUARTEnable.reg |= pairUARTEnable.mask; //Enable UART line
}
void UART::begin(uint32_t baudRate) volatile {
USART_TypeDef* usart = getUARTPair(m_UARTPair).USARTReg;
usart->CR1 &= ~USART_CR1_UE; //Disable USART
usart->CR1 = 0; //Clear USART config
usart->CR1 = USART_CR1_TE | USART_CR1_RE; //Tx enable and Rx Enable
usart->BRR = 8000000 / baudRate; //MAKE SURE ANY FUNCTION THAT CHANGES CLOCK UPDATES THIS!
usart->CR1 |= USART_CR1_UE;
}
void UART::sendString(const char *s) volatile {
while (*s) sendChar(*s++); //Send chars while we haven't reached end of s
}
void UART::sendChar(char c) volatile {
USART_TypeDef* usart = getUARTPair(m_UARTPair).USARTReg;
while(!(usart->ISR & USART_ISR_TXE)); //Wait for usart to finish what it's doing
usart->TDR = c; //Send character
}
UART& UARTManager::get(UART_Pair pair) {
//Reassign if pair doesn't match
if(m_UARTs[getUARTChannel(pair)].m_UARTPair != pair) {
m_UARTs[getUARTChannel(pair)] = UART(pair);
}
return m_UARTs[getUARTChannel(pair)];
}

View File

@@ -0,0 +1,42 @@
//
// Created by Luca on 9/15/2025.
//
#include "SHAL_CORE.h"
void SHAL_init(){
systick_init(); //Just this for now
}
void systick_init(){
SysTick->CTRL = 0; //Disable first
SysTick->LOAD = 0xFFFFFF; //Max 24-bit
SysTick->VAL = 0; //Clear
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
}
void SHAL_delay_us(uint32_t us){
uint32_t ticks = us * (SystemCoreClock / 1000000U);
uint32_t start = SysTick->VAL;
//Calculate target value (may wrap around)
uint32_t target = (start >= ticks) ? (start - ticks) : (start + 0x01000000 - ticks);
target &= 0x00FFFFFF;
//Wait until we reach the target
if (start >= ticks) {
//No wraparound case
while (SysTick->VAL > target) {}
} else {
while (SysTick->VAL <= start) {} //Wait for wraparound
while (SysTick->VAL > target) {} //Wait for target
}
}
void SHAL_delay_ms(uint32_t ms){
while(ms-- > 0){
SHAL_delay_us(1000);
}
}

View File

@@ -0,0 +1,115 @@
//
// Created by Luca on 9/21/2025.
//
#include "SHAL_ADC.h"
//Can hard code registers on F0 because all F0 devices have only one ADC, and use only one clock
SHAL_Result SHAL_ADC::init() {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return SHAL_Result::ERROR;
}
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; //Enable clock
RCC->CR2 |= RCC_CR2_HSI14ON; //Start peripheral oscillator
if(!SHAL_WAIT_FOR_CONDITION_US(((RCC->CR2 & RCC_CR2_HSI14RDY) != 0),50)){ //Wait for clock OKAY
return SHAL_Result::ERROR;
}
if((ADC_reg->ISR & ADC_ISR_ADRDY) != 0){ //Set ADRDY to 0
ADC_reg->ISR |= ADC_ISR_ADRDY;
}
ADC_reg->CR |= ADC_CR_ADEN; //Enable
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_ADRDY) != 0),50)){ //Wait for disable
return SHAL_Result::ERROR;
}
if(calibrate() != SHAL_Result::OKAY){ //Calibrate
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::calibrate() {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return SHAL_Result::ERROR;
}
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
if((ADC_reg->CR & ADC_CR_ADEN) != 0){ //Clear ADEN (enable)
ADC_reg->CR |= ADC_CR_ADDIS;
}
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->CR & ADC_CR_ADEN) == 0),50)){ //Wait for disable
return SHAL_Result::ERROR;
}
ADC_reg->CFGR1 &= ~ADC_CFGR1_DMAEN; //Clear DMAEN
ADC_reg->CR |= ADC_CR_ADCAL; //Launch calibration by setting ADCAL
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->CR & ADC_CR_ADCAL) == 0),50)){ //Wait for calibration
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
uint16_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_TSEN; //Enable VREFINT and Temp sensor in global ADC struct
ADC_reg->CHSELR = static_cast<uint32_t>(channel); //Enable channel for conversion
ADC_reg->SMPR |= static_cast<uint32_t>(time); //Set sampling time
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_EOC) != 0),500)){ //Wait for conversion
return 0; //Failed
}
uint16_t result = ADC_reg->DR;
return result;
}
void SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, const int numChannels, uint16_t* result, SHAL_ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_TSEN; //Enable VREFINT and Temp sensor in global ADC struct
for(int i = 0; i < numChannels; i++){ //Enable all channels
ADC_reg->CHSELR = static_cast<uint32_t>(channels[i]);
}
ADC_reg->SMPR |= static_cast<uint32_t>(time); //Set sampling time
for(int i = 0; i < numChannels; i++){
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_EOC) != 0),500)){ //Wait for conversion
continue; //Failed
}
result[i] = ADC_reg->DR;
}
}
SHAL_ADC &ADCManager::get(ADC_Key key) {
return m_ADCs[static_cast<uint8_t>(key)];
}
SHAL_ADC& ADCManager::getByIndex(int index) {
if(index < static_cast<int>(ADC_Key::NUM_ADC)){
return m_ADCs[index];
}
return m_ADCs[0];
}

View File

@@ -0,0 +1,128 @@
//
// Created by Luca on 8/30/2025.
//
#include "SHAL_GPIO.h"
#include "SHAL_EXTI_CALLBACK.h"
SHAL_GPIO::SHAL_GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
volatile unsigned long* gpioEnable = getGPIORCCEnable(key).reg;
unsigned long gpioOffset = getGPIORCCEnable(key).offset;
*gpioEnable |= (1 << gpioOffset); //Set enable flag
}
void SHAL_GPIO::setLow() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR &= ~(1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setHigh() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR |= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::toggle() volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR ^= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setPinType(PinType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OTYPER &= ~(1 << gpioPeripheral.global_offset);
gpioPeripheral.reg->OTYPER |= (static_cast<uint8_t>(type) << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OSPEEDR |= (static_cast<uint8_t>(speed) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setInternalResistor(InternalResistorType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->PUPDR &= ~(0x03 << (2 * gpioPeripheral.global_offset));
gpioPeripheral.reg->PUPDR |= (static_cast<uint8_t>(type) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
int afrIndex = gpioPeripheral.global_offset < 8 ? 0 : 1; //Get index of AFR
gpioPeripheral.reg->AFR[afrIndex] &= ~(0xF << (gpioPeripheral.global_offset * 4));
gpioPeripheral.reg->AFR[afrIndex] |= (static_cast<int>(AF) << (gpioPeripheral.global_offset * 4));
}
void SHAL_GPIO::setPinMode(PinMode mode) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->MODER &= ~(0x03 << (2 * gpioPeripheral.global_offset)); //Clear any previous mode
gpioPeripheral.reg->MODER |= (static_cast<uint8_t>(mode) << (2 * gpioPeripheral.global_offset)); //Set mode based on pinmode bit structure
}
void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {
uint32_t gpioPin = getGPIORegister(m_GPIO_KEY).global_offset; //Use existing structs to get offset
setPinMode(PinMode::INPUT_MODE); //Explicitly set mode to input
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; //Enable EXT, TODO check if this is different across STM32 models
NVIC_EnableIRQ(getGPIOEXTICR(m_GPIO_KEY).IRQN); //Enable IRQN for pin
EXTI->IMR |= (1 << gpioPin); //Enable correct EXTI line
SHAL_EXTIO_Register EXTILineEnable = getGPIOEXTICR(m_GPIO_KEY);
*EXTILineEnable.EXT_ICR |= EXTILineEnable.mask; //Set bits to enable correct port on correct line TODO Find way to clear bits before
uint32_t rising_mask = 0x00;
uint32_t falling_mask = 0x00;
//Set rising and falling edge triggers based on pin offset (enabled EXTI line)
switch(mode){
case TriggerMode::RISING_EDGE:
rising_mask = 1 << gpioPin;
break;
case TriggerMode::FALLING_EDGE:
falling_mask = 1 << gpioPin;
break;
case TriggerMode::RISING_FALLING_EDGE:
falling_mask = 1 << gpioPin;
falling_mask = 1 << gpioPin;
}
//Set triggers
EXTI->RTSR |= rising_mask;
EXTI->FTSR |= falling_mask;
//Set callback
registerEXTICallback(m_GPIO_KEY,callback);
__enable_irq(); //Enable IRQ just in case
}
uint16_t SHAL_GPIO::analogRead(SHAL_ADC_SampleTime sampleTime) {
SHAL_ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
}
SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
unsigned int gpioPort = getGPIOPortNumber(key);
unsigned long gpioPin = getGPIORegister(key).global_offset; //Use existing structs to get offset
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
}
return m_gpios[gpioPort][gpioPin];
}

View File

@@ -0,0 +1,142 @@
//
// Created by Luca on 9/9/2025.
//
#include "SHAL_I2C.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART.h"
void SHAL_I2C::init(I2C_Pair pair) volatile {
m_I2CPair = pair;
SHAL_I2C_Pair I2CPair = getI2CPair(pair); //Get the I2C_PAIR information to be initialized
//Get the SHAL_GPIO pins for this SHAL_I2C setup
GPIO_Key SCL_Key = I2CPair.SCL_Key; //SCL pin
GPIO_Key SDA_Key = I2CPair.SDA_Key; //SDA pin
SHAL_I2C_Enable_Reg pairI2CEnable = getI2CEnableReg(pair); //Register and mask to enable the I2C peripheral
*pairI2CEnable.reg &= ~pairI2CEnable.mask; //Enable I2C peripheral clock
GET_GPIO(SCL_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE); //Implicitly initializes and enables GPIO bus
GET_GPIO(SDA_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
GET_GPIO(SCL_Key).setAlternateFunction(I2CPair.SCL_Mask);
GET_GPIO(SDA_Key).setAlternateFunction(I2CPair.SDA_Mask);
//These may be abstracted further to support multiple I2C configurations
GET_GPIO(SCL_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SDA_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SCL_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
GET_GPIO(SDA_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
GET_GPIO(SCL_Key).setInternalResistor(InternalResistorType::PULLUP);
GET_GPIO(SDA_Key).setInternalResistor(InternalResistorType::PULLUP);
SHAL_I2C_Reset_Reg pairI2CReset = getI2CResetReg(pair);
*pairI2CEnable.reg |= pairI2CEnable.mask; //Enable I2C peripheral clock
*pairI2CReset.reg |= pairI2CReset.mask; //Reset peripheral
*pairI2CReset.reg &= ~pairI2CReset.mask; //Reset peripheral
}
void SHAL_I2C::setClockConfig(uint8_t prescaler, uint8_t dataSetupTime, uint8_t dataHoldTime, uint8_t SCLHighPeriod, uint8_t SCLLowPeriod) {
SHAL_I2C_Timing_Reg clockReg = getI2CTimerReg(m_I2CPair);
*clockReg.reg |= (prescaler << clockReg.prescaler_offset);
*clockReg.reg |= (dataSetupTime << clockReg.dataSetupTime_offset);
*clockReg.reg |= (dataHoldTime << clockReg.dataHoldTime_offset);
*clockReg.reg |= (SCLHighPeriod << clockReg.SCLHighPeriod_offset);
*clockReg.reg |= (SCLLowPeriod << clockReg.SCLLowPeriod_offset);
getI2CPair(m_I2CPair).I2CReg->CR1 |= I2C_CR1_PE; //Enable I2C peripheral
}
void SHAL_I2C::setClockConfig(uint32_t configuration) {
*getI2CTimerReg(m_I2CPair).reg = configuration;
getI2CPair(m_I2CPair).I2CReg->CR1 |= I2C_CR1_PE; //Enable I2C peripheral
}
void SHAL_I2C::masterWriteRead(uint8_t addr,const uint8_t* writeData, size_t writeLen, uint8_t* readData, size_t readLen) {
volatile I2C_TypeDef* I2CPeripheral = getI2CPair(m_I2CPair).I2CReg;
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_BUSY) == 0, 100)){
SHAL_UART2.sendString("I2C timed out waiting for not busy\r\n");
return;
}
//Write phase
if (writeLen > 0) {
//Configure: NBYTES = wlen, write mode, START
I2CPeripheral->CR2 = (addr << 1) | (writeLen << I2C_CR2_NBYTES_Pos) | I2C_CR2_START;
for (size_t i = 0; i < writeLen; i++) {
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_TXIS) != 0, 100)){
SHAL_UART2.sendString("I2C timed out waiting for TX\r\n");
return;
}
I2CPeripheral->TXDR = writeData[i];
}
//Wait until transfer complete
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_TC) != 0, 100)){
SHAL_UART2.sendString("I2C timed out waiting for TC\r\n");
return;
}
}
//Read phase
if (readLen > 0) {
SHAL_UART2.sendString("Read initiated\r\n");
I2CPeripheral->CR2 &= ~(I2C_CR2_NBYTES | I2C_CR2_SADD | I2C_CR2_RD_WRN);
I2CPeripheral->CR2 |= (addr << 1) |
I2C_CR2_RD_WRN |
(readLen << I2C_CR2_NBYTES_Pos) |
I2C_CR2_START | I2C_CR2_AUTOEND;
for (size_t i = 0; i < readLen; i++) {
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_RXNE) != 0 , 100)){
SHAL_UART2.sendString("I2C timed out waiting for RXNE\r\n");
return;
}
SHAL_UART2.sendString("Read byte");
readData[i] = static_cast<uint8_t>(I2CPeripheral->RXDR);
}
}
else{
I2CPeripheral->CR2 |= I2C_CR2_STOP;
}
}
void SHAL_I2C::masterWrite(uint8_t addr, const uint8_t *writeData, uint8_t writeLen) {
masterWriteRead(addr,writeData,writeLen,nullptr,0);
}
void SHAL_I2C::masterRead(uint8_t addr, uint8_t *readBuffer, uint8_t bytesToRead) {
masterWriteRead(addr,nullptr,0,readBuffer,bytesToRead);
}
uint8_t SHAL_I2C::masterWriteReadByte(uint8_t addr, const uint8_t *writeData, size_t writeLen) {
uint8_t val = 0;
masterWriteRead(addr, writeData, writeLen, &val, 1);
return val;
}
SHAL_I2C& I2CManager::get(uint8_t I2CBus) {
if(I2CBus > NUM_I2C_BUSES - 1){
assert(false);
//Memory fault
}
return m_I2CBuses[I2CBus];
}

View File

@@ -6,8 +6,7 @@
#include <cassert>
Timer::Timer(Timer_Key t) : TIMER_KEY(t){
TIM_RCC_Enable rcc = getTimerRCC(TIMER_KEY);
*rcc.busEnableReg |= (1 << rcc.offset);
}
Timer::Timer() : TIMER_KEY(Timer_Key::S_TIM_INVALID){
@@ -37,6 +36,14 @@ void Timer::enableInterrupt() {
NVIC_EnableIRQ(getIRQn(TIMER_KEY));
}
void Timer::init(uint32_t prescaler, uint32_t autoReload) {
TIM_RCC_Enable rcc = getTimerRCC(TIMER_KEY);
*rcc.busEnableReg |= (1 << rcc.offset);
setPrescaler(prescaler);
setARR(autoReload);
}
Timer &TimerManager::get(Timer_Key timer_key) {
@@ -52,3 +59,5 @@ Timer &TimerManager::get(Timer_Key timer_key) {
return timers[static_cast<int>(timer_key)];
}

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