271 lines
8.1 KiB
C++
271 lines
8.1 KiB
C++
//
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// Created by Luca on 9/21/2025.
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//
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#include "SHAL_ADC.h"
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#include "SHAL_GPIO.h"
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#include "SHAL_UART.h"
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#include <cstdio>
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bool SHAL_ADC::isValid() const {
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if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
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return false;
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}
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return true;
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}
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SHAL_Result SHAL_ADC::init(const ADC_Key key, SHAL_ADC_Sample_Mode mode){
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m_ADCKey = key;
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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auto rcc = getADCRCCEnableRegister(m_ADCKey); //Clock enable
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auto ccr = getADCCommonControl(m_ADCKey);
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SHAL_apply_bitmask(rcc.reg,rcc.mask); //Enable clock
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wakeFromDeepSleep(); //Wake and enable LDO
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//Configure clock source
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SHAL_set_bits(ccr.reg,2,static_cast<uint32_t>(SHAL_ADC_Clock_Mode::SYNC_BY_2),ccr.clock_mode_position); //TODO take as param?
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configureResolution(SHAL_ADC_Resolution::B12); //Configure resolution
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SHAL_apply_bitmask(ccr.reg,ccr.VoltageRefEnable);
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if(calibrate(mode) != SHAL_Result::OKAY){ //Calibrate
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return SHAL_Result::ERROR;
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}
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if(enable() != SHAL_Result::OKAY){
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return SHAL_Result::ERROR;
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}
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::calibrate(SHAL_ADC_Sample_Mode sampleMode) const {
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const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
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if(disable() != SHAL_Result::OKAY){
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return SHAL_Result::ERROR;
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}
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SHAL_set_bits(control_reg.reg, 1, static_cast<uint32_t>(sampleMode), control_reg.sample_mode_offset); //Set sample mode (differential or single ended)
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SHAL_apply_bitmask(control_reg.reg, control_reg.calibration_mask); //Start calibration
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if (!SHAL_wait_for_bit_clear_us(control_reg.reg, control_reg.calibration_mask, 100)) { //Wait for calibration
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return SHAL_Result::ERROR;
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}
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return SHAL_Result::OKAY;
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}
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uint32_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time) const {
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auto data_reg = getADCDataReg(m_ADCKey);
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auto ISR_reg = getADCISRReg(m_ADCKey);
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auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey, channel);
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SHAL_set_bits(sampleTimeReg.reg, 3, static_cast<uint8_t>(time), sampleTimeReg.channel_offset); //Set sample time
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if(setADCSequenceAmount(1) == SHAL_Result::ERROR) { return 0; } //Set sequence amount to 1
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addADCChannelToSequence(channel, 1);
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startConversion();
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if (!SHAL_wait_for_bit_set_us(ISR_reg.reg, ISR_reg.end_of_conversion_mask, 200)) {
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return 0;
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}
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uint32_t result = *data_reg.reg;
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return result;
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}
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SHAL_Result SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time) {
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auto data_reg = getADCDataReg(m_ADCKey); //Where our output will be stored
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setADCSequenceAmount(numChannels); //Convert the correct amount of channels
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for(int i = 0; i < numChannels; i++){
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auto channel = channels[i];
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auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey,channel);
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SHAL_set_bits(sampleTimeReg.reg,3,static_cast<uint8_t>(time),sampleTimeReg.channel_offset); //Set sample time register TODO un-hardcode bit width?
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addADCChannelToSequence(channel,i); //Use index 0 to convert channel
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}
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startConversion(); //Start ADC conversion
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auto ISR_reg = getADCISRReg(m_ADCKey);
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for(int i = 0; i < numChannels; i++) {
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if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_conversion_mask) != 0),500)) { //Wait for conversion
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return SHAL_Result::ERROR; //Failed conversion
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}
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result[i] = *data_reg.reg;
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}
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if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_sequence_mask) != 0),500)) { //Wait for conversion
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return SHAL_Result::ERROR; //Failed sequence
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}
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::enable() const {
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
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const SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
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SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask); //Clear ready flag (write is correct as per datasheet)
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SHAL_apply_bitmask(control_reg.reg, control_reg.enable_mask); //Enable mask
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if (!SHAL_wait_for_bit_set_us(ISR_reg.reg,ISR_reg.ready_mask,500)) { //Check ADRDY
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return SHAL_Result::ERROR;
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}
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return SHAL_Result::OKAY;
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}
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/// Disables the ADC
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/// @return
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SHAL_Result SHAL_ADC::disable() const {
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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const auto control_reg = getADCControlReg(m_ADCKey);
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//Stop any ongoing conversion
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if (SHAL_check_bit(control_reg.reg, control_reg.start_mask)) {
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SHAL_apply_bitmask(control_reg.reg, control_reg.stop_mask);
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}
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if (SHAL_check_bit(control_reg.reg,control_reg.enable_mask)) { //DO NOT disable if the ADC is already disabled
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SHAL_apply_bitmask(control_reg.reg, control_reg.disable_mask);
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if (!SHAL_wait_for_bit_clear_ms(control_reg.reg,(control_reg.enable_mask | control_reg.disable_mask),50)) {
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return SHAL_Result::ERROR;
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}
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}
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::wakeFromDeepSleep() const {
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const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey); //ADC Control register
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const SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
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SHAL_clear_bitmask(control_reg.reg,control_reg.deep_power_down_mask); //Wake ADC from sleep
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SHAL_apply_bitmask(control_reg.reg,control_reg.voltage_regulator_mask);
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if (!SHAL_wait_for_bit_set_us(ISR_reg.reg,ISR_reg.ldo_ready_mask,50)) { //Wait for LDO
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return SHAL_Result::ERROR;
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}
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::startConversion() const {
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auto control_reg = getADCControlReg(m_ADCKey);
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SHAL_apply_bitmask(control_reg.reg,control_reg.start_mask);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::configureResolution(SHAL_ADC_Resolution resolution) const {
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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const SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
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/*
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SHAL_set_bits(config_reg.reg,2,static_cast<uint8_t>(resolution),config_reg.resolution_offset);
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char buff[20];
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snprintf(buff,16,"CFGR: %lu\r\n", (unsigned long)ADC1->CFGR);
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SHAL_UART3.sendString(buff);
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*/
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SHAL_set_register_value(config_reg.reg, 0);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::configureAlignment(SHAL_ADC_Alignment alignment) const {
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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const SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
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//TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
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SHAL_set_bits(config_reg.reg,1,static_cast<uint8_t>(alignment),config_reg.alignment_offset);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::preselectChannel(SHAL_ADC_Channel channel) const {
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auto preselect = getADCPreselectRegister(ADC_Key::S_ADC1, SHAL_ADC_Channel::CH15);
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SHAL_set_bits(preselect.reg,1,1,preselect.channel_offset);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::setADCSequenceAmount(uint32_t amount) const {
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if(!isValid()){return SHAL_Result::ERROR;}
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if(amount == 0){
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return SHAL_Result::ERROR;
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}
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SHAL_ADC_Sequence_Amount_Reg sequence_amount_reg = getADCSequenceAmountRegister(m_ADCKey);
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SHAL_set_bits(sequence_amount_reg.reg, 4, amount - 1, 0); //Sequence amount reg is just SQR1 least significant 4 bits, this offset should always be 0
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::addADCChannelToSequence(SHAL_ADC_Channel channel, const uint32_t conversionNumber) const {
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if(!isValid()) { return SHAL_Result::ERROR; }
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auto sqr = getADCSequenceRegister(m_ADCKey, conversionNumber);
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auto channelNum = static_cast<uint8_t>(channel);
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SHAL_wait_for_bit_clear_ms(&ADC1->CR,ADC_CR_ADSTART,50);
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SHAL_set_bits(sqr.reg, 5, channelNum, sqr.sequence_offset); //Set regular sequence register
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return SHAL_Result::OKAY;
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}
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SHAL_ADC &ADCManager::get(ADC_Key key) {
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return m_ADCs[static_cast<uint8_t>(key)];
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}
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SHAL_ADC& ADCManager::getByIndex(int index) {
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if(index < static_cast<int>(ADC_Key::NUM_ADC)){
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return m_ADCs[index];
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}
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return m_ADCs[0];
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} |