205 lines
6.4 KiB
C
205 lines
6.4 KiB
C
/**
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******************************************************************************
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* @file SHAL_TIM_REG.h
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* @author Luca Lizaranzu
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* @brief Defines universal macros and objects used across all STM32 families
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******************************************************************************
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*/
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#ifndef SHAL_TIM_REG_L432KC_H
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#define SHAL_TIM_REG_L432KC_H
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#include <cassert>
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#include <stm32l432xx.h>
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#include "SHAL_CORE.h"
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#include "SHAL_TIM_TYPES.h"
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enum class Timer_Key : uint8_t { //For STM32L432
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S_TIM1,
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S_TIM2,
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S_TIM6,
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S_TIM7,
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S_TIM15,
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S_TIM16,
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NUM_TIMERS,
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S_TIM_INVALID
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};
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//Lookup table for timer typedefs
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static volatile TIM_TypeDef* TIM_TABLE[6] = {
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TIM1,
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TIM2,
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TIM6,
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TIM7,
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TIM15,
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TIM16,
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};
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static IRQn_Type IRQN_TABLE[6] = {
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TIM1_TRG_COM_IRQn,
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TIM2_IRQn,
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TIM6_DAC_IRQn,
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TIM7_IRQn,
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TIM1_BRK_TIM15_IRQn,
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TIM1_UP_TIM16_IRQn
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};
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#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
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#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
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#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
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#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
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#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
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#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
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static inline SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
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SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->SR;
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return res;
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}
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static inline SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
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SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk,
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TIM_CR1_UDIS,
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TIM_CR1_OPM,
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TIM_CR1_CMS_Pos,
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TIM_CR1_ARPE};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->CR1;
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return res;
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}
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static inline SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
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SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->DIER;
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return res;
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}
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static inline SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
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SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->EGR;
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return res;
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}
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static inline SHAL_TIM_Prescaler_Register getTimerPrescalerRegister(Timer_Key key){
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SHAL_TIM_Prescaler_Register res = {nullptr, 1UL << 15};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->PSC;
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return res;
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}
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static inline SHAL_TIM_Auto_Reload_Register getTimerAutoReloadRegister(Timer_Key key){
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SHAL_TIM_Auto_Reload_Register res = {nullptr, 1UL << 15};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->ARR;
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return res;
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}
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//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
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static inline SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
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switch(t) {
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case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
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case Timer_Key::S_TIM2: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN};
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case Timer_Key::S_TIM6: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN};
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case Timer_Key::S_TIM7: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN};
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case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
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case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
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case Timer_Key::NUM_TIMERS:
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case Timer_Key::S_TIM_INVALID:
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assert(false);
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}
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__builtin_unreachable();
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}
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static inline SHAL_TIM_Capture_Compare_Mode_Registers_Input getTimerCaptureCompareModeRegisters(Timer_Key key){
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SHAL_TIM_Capture_Compare_Mode_Registers_Input res = {{nullptr,
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nullptr},
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TIM_CCMR1_CC1S_Pos,
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TIM_CCMR1_IC1PSC_Pos,
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TIM_CCMR1_IC1F_Pos,
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TIM_CCMR1_CC2S_Pos,
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TIM_CCMR1_IC2PSC_Pos,
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TIM_CCMR1_IC2F_Pos
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};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.regs[0] = &tim->CCMR1;
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res.regs[1] = &tim->CCMR2;
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return res;
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}
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static inline SHAL_TIM_Capture_Compare_Mode_Registers_Output
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getTimerCaptureCompareModeRegistersOutput(Timer_Key key) {
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SHAL_TIM_Capture_Compare_Mode_Registers_Output res = {
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{nullptr, nullptr},
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TIM_CCMR1_CC1S_Pos, //Channel 1 Capture/Compare selection
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TIM_CCMR1_OC1FE_Pos, //Channel 1 Fast enable
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TIM_CCMR1_OC1PE_Pos, //Channel 1 Preload enable
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TIM_CCMR1_OC1M_Pos, //Channel 1 Mode (OC1M)
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TIM_CCMR1_OC1CE_Pos, //Channel 1 Clear enable
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TIM_CCMR1_CC2S_Pos, //Channel 2 Capture/Compare selection
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TIM_CCMR1_OC2FE_Pos, //Channel 2 Fast enable
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TIM_CCMR1_OC2PE_Pos, //Channel 2 Preload enable
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TIM_CCMR1_OC2M_Pos, //Channel 2 Mode (OC2M)
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TIM_CCMR1_OC2CE_Pos //Channel 2 Clear enable
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};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.regs[0] = &tim->CCMR1;
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res.regs[1] = &tim->CCMR2;
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return res;
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}
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static inline SHAL_TIM_Break_Dead_Time_Register getBreakDeadTimeRegister(Timer_Key key){
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SHAL_TIM_Break_Dead_Time_Register res = {nullptr, 1UL << 15};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->BDTR;
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return res;
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}
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static inline SHAL_TIM_Capture_Compare_Enable_Register getTimerCaptureCompareEnableRegister(Timer_Key key){
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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return {&tim->CCER};
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}
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static inline SHAL_TIM_Capture_Compare_Register getTimerCaptureCompareRegister(Timer_Key key){
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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return {&tim->CCR2};
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}
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//Get timer IRQN from lookup table
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static inline IRQn_Type getTimerIRQn(Timer_Key t) {
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return IRQN_TABLE[static_cast<uint8_t>(t)];
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}
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#endif |