122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
/**
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******************************************************************************
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* @file SHAL_TIM_REG.h
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* @author Luca Lizaranzu
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* @brief Defines universal macros and objects used across all STM32 families
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******************************************************************************
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*/
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#ifndef SHAL_TIM_REG_L432KC_H
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#define SHAL_TIM_REG_L432KC_H
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#include <cassert>
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#include <stm32l432xx.h>
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#include "SHAL_CORE.h"
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#include "SHAL_TIM_TYPES.h"
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enum class Timer_Key : uint8_t { //For STM32L432
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S_TIM1,
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S_TIM2,
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S_TIM6,
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S_TIM7,
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S_TIM15,
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S_TIM16,
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NUM_TIMERS,
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S_TIM_INVALID
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};
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//Lookup table for timer typedefs
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static volatile TIM_TypeDef* TIM_TABLE[6] = {
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TIM1,
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TIM2,
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TIM6,
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TIM7,
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TIM15,
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TIM16,
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};
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#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
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#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
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#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
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#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
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#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
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#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
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static inline SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
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SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->SR;
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return res;
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}
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static inline SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
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SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk, TIM_CR1_UDIS, TIM_CR1_OPM, TIM_CR1_CMS_Pos};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->CR1;
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return res;
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}
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static inline SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
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SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->CR1;
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return res;
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}
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static inline SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
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SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
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volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
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res.reg = &tim->CR1;
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return res;
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}
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//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
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static inline SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
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switch(t) {
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case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_Pos};
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case Timer_Key::S_TIM2: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN_Pos};
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case Timer_Key::S_TIM6: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN_Pos};
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case Timer_Key::S_TIM7: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN_Pos};
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case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN_Pos};
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case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN_Pos};
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case Timer_Key::NUM_TIMERS:
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case Timer_Key::S_TIM_INVALID:
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assert(false);
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}
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__builtin_unreachable();
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}
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static inline IRQn_Type getTimerIRQn(Timer_Key t) {
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switch(t) {
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case Timer_Key::S_TIM1: return TIM1_TRG_COM_IRQn;
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case Timer_Key::S_TIM2: return TIM2_IRQn;
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case Timer_Key::S_TIM6: return TIM6_DAC_IRQn;
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case Timer_Key::S_TIM7: return TIM7_IRQn;
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case Timer_Key::S_TIM15: return TIM1_BRK_TIM15_IRQn;
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case Timer_Key::S_TIM16: return TIM1_UP_TIM16_IRQn;
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case Timer_Key::NUM_TIMERS:
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case Timer_Key::S_TIM_INVALID:
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__builtin_unreachable();
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}
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__builtin_unreachable();
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}
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#endif |