172 lines
4.1 KiB
C++
172 lines
4.1 KiB
C++
//
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// Created by Luca on 10/8/2025.
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//
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#ifndef SHMINGO_HAL_SHAL_ADC_REG_L432KC_H
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#define SHMINGO_HAL_SHAL_ADC_REG_L432KC_H
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#include "SHAL_CORE.h"
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#include "SHAL_ADC_TYPES.h"
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#define SHAL_ADC1 SHAL_ADC(1)
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#define NUM_ADCS 1
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#define NUM_ADC_CHANNELS 16
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enum class SHAL_ADC_Channel : uint32_t {
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CH0 = 0,
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CH1,
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CH2,
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CH3,
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CH4,
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CH5,
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CH6,
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CH7,
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CH8,
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CH9,
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CH10,
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CH11,
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CH12,
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CH13,
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CH14,
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CH15,
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CH16,
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CHTemp,
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CHRef,
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CHBat,
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NO_ADC_MAPPING
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};
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enum class ADC_Key : uint8_t{
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S_ADC1 = 0,
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NUM_ADC = 1,
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INVALID = 255
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};
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enum class ADC_Clock_Source : uint32_t {
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SHAL_NO_CLOCK = 0x00,
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SHAL_PLLSAI1 = 0x01,
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SHAL_PLLSYS = 0x02,
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SHAL_SYSCLK = 0x03,
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};
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static volatile ADC_TypeDef* ADC_TABLE[1] = { //Lookup table for ADCs
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ADC1,
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};
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static inline SHAL_ADC_Common_Control_Reg getADCCommonControl() {
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return {&ADC1_COMMON->CCR ,ADC_CCR_VREFEN,ADC_CCR_TSEN,ADC_CCR_VBATEN};
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}
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static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
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SHAL_ADC_RCC_Enable_Reg res = {&RCC->AHB2ENR, RCC_AHB2ENR_ADCEN};
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return res;
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}
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static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
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SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN,
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ADC_CR_ADSTP,
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ADC_CR_ADDIS,
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ADC_CR_ADCAL,
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ADC_CR_ADSTART,
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ADC_CR_DEEPPWD,
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ADC_CR_ADVREGEN,
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ADC_CR_ADCALDIF};
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res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
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return res;
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}
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static inline SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
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SHAL_ADC_Config_Reg res = {nullptr, ADC_CFGR_CONT, ADC_CFGR_RES_Pos, ADC_CFGR_ALIGN_Pos};
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res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CFGR);
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return res;
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}
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static inline SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
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SHAL_ADC_ISR_Reg res = {nullptr, ADC_ISR_EOC, ADC_ISR_EOS, ADC_ISR_ADRDY};
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res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
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return res;
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}
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static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
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SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
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res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
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return res;
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}
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static inline SHAL_ADC_Clock_Reg getADCClockSelectRegister() {
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SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Pos}; //Position
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return res;
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}
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static inline SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
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volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
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volatile uint32_t* SMPReg = nullptr;
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uint32_t pos;
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auto channelNum = static_cast<uint8_t>(channel);
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if (channelNum <= 9) {
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SMPReg = &ADCReg->SMPR1;
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pos = (channelNum * 3);
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} else {
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SMPReg = &ADCReg->SMPR2;
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pos = ((channelNum - 10) * 3);
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}
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return {SMPReg, pos};
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}
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static inline SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
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SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
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res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
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return res;
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}
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static inline SHAL_ADC_Sequence_Reg getADCSequenceRegisters(ADC_Key key){
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volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];
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SHAL_ADC_Sequence_Reg res = {{&adc_reg->SQR1,
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&adc_reg->SQR2,
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&adc_reg->SQR3,
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&adc_reg->SQR4,
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nullptr,
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nullptr},
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{0,
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6,
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12,
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18,
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24}
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};
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return res;
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}
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constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
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switch(key){
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case ADC_Key::S_ADC1:
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return ADC1;
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case ADC_Key::NUM_ADC:
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case ADC_Key::INVALID:
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return nullptr;
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}
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__builtin_unreachable();
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}
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#endif //SHMINGO_HAL_SHAL_ADC_REG_L432KC_H
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