110 lines
3.6 KiB
C++
110 lines
3.6 KiB
C++
//
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// Created by Luca on 8/28/2025.
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//
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#include "SHAL_TIM.h"
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#include <cassert>
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Timer::Timer(Timer_Key key) : m_key(key){
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}
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Timer::Timer() : m_key(Timer_Key::S_TIM_INVALID){
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}
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void Timer::start() {
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auto control_reg = getTimerControlRegister1(m_key);
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auto event_generation_reg = getTimerEventGenerationRegister(m_key);
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SHAL_apply_bitmask(control_reg.reg, control_reg.counter_enable_mask); //Enable counter
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SHAL_apply_bitmask(control_reg.reg, control_reg.auto_reload_preload_enable_mask); //Preload enable (buffer)
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SHAL_apply_bitmask(event_generation_reg.reg, event_generation_reg.update_generation_mask);
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enableInterrupt();
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}
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void Timer::stop() {
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auto control_reg = getTimerControlRegister1(m_key);
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SHAL_clear_bitmask(control_reg.reg, control_reg.counter_enable_mask); //Enable counter
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}
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void Timer::setPrescaler(uint16_t presc) {
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auto prescaler_reg = getTimerPrescalerRegister(m_key);
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SHAL_set_register_value(prescaler_reg.reg,presc);
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}
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void Timer::setARR(uint16_t arr) {
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auto autoreload_reg = getTimerAutoReloadRegister(m_key);
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SHAL_set_register_value(autoreload_reg.reg,arr);
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}
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void Timer::enableInterrupt() {
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auto dma_ier = getTimerDMAInterruptEnableRegister(m_key);
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SHAL_apply_bitmask(dma_ier.reg,dma_ier.update_interrupt_enable_mask);
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NVIC_EnableIRQ(getTimerIRQn(m_key)); //Enable the IRQn in the NVIC
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}
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void Timer::init(uint32_t prescaler, uint32_t autoReload) {
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SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);
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SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
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setPrescaler(prescaler);
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setARR(autoReload);
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}
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void Timer::setPWMMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode, SHAL_Timer_Channel_Main_Output_Mode mainOutputMode,
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SHAL_Timer_Channel_Complimentary_Output_Mode complimentaryOutputMode) {
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auto ccer = getTimerCaptureCompareEnableRegister(m_key);
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auto ccmr1 = getTimerCaptureCompareModeRegistersOutput(m_key);
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auto bdtr = getTimerBreakDeadTimeRegister(m_key);
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uint8_t fullChannelModeMask = static_cast<uint8_t>(mainOutputMode) | (static_cast<uint8_t>(complimentaryOutputMode) << 2);
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uint8_t channelNum = static_cast<uint8_t>(channel);
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if (channelNum <= 3) {
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uint32_t regNum = channelNum / 2; //TODO change later for support for channels 5 and 6
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if (channelNum % 2 == 1) {
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SHAL_set_bits(ccmr1.regs[regNum], 4, static_cast<uint8_t>(outputCompareMode),
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ccmr1.output_compare_2_mode_offset);
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} else {
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SHAL_set_bits(ccmr1.regs[regNum], 4, static_cast<uint8_t>(outputCompareMode),
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ccmr1.output_compare_1_mode_offset);
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}
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}
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uint32_t offset = channelNum * 4;
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if (static_cast<uint8_t>(m_key) > 3) {
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fullChannelModeMask &= (0b0011); //Clear bits for complimentary output since channels 4,5,6 don't support it
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}
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SHAL_set_bits(ccer.reg, 4, fullChannelModeMask, offset);
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SHAL_apply_bitmask(bdtr.reg, bdtr.main_output_enable_mask);
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}
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void Timer::setPWMDutyCycle(uint32_t dutyCycle) {
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auto reg = getTimerCaptureCompareRegister(m_key);
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SHAL_set_bits(reg.reg,16,dutyCycle,0);
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}
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Timer &TimerManager::get(Timer_Key timer_key) {
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//Ensure that we don't try to get invalid timers
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assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
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Timer& selected = timers[static_cast<int>(timer_key)];
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//Timer queried is not initialized yet (defaults to invalid)
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if(selected.m_key == Timer_Key::S_TIM_INVALID){
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timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
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}
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return timers[static_cast<int>(timer_key)];
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} |