297 lines
8.8 KiB
C++
297 lines
8.8 KiB
C++
//
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// Created by Luca on 9/21/2025.
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//
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#include "SHAL_ADC.h"
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#include "SHAL_GPIO.h"
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#include "SHAL_UART.h"
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#include <cstdio>
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SHAL_Result SHAL_ADC::init(ADC_Key key) {
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m_ADCKey = key;
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if(!isValid()){
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SHAL_UART2.sendString("Not valid\r\n");
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return SHAL_Result::ERROR;
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}
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SHAL_ADC_RCC_Enable_Reg clock_reg = getADCRCCEnableRegister(m_ADCKey); //Clock enable
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SHAL_apply_bitmask(clock_reg.reg,clock_reg.mask);
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auto clock_select_register = getADCClockSelectRegister();
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SHAL_set_bits(clock_select_register.reg, 2, static_cast<uint32_t>(ADC_Clock_Source::SHAL_SYSCLK),clock_select_register.offset); //Set ADC clock
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wakeFromDeepSleep();
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if(calibrate() != SHAL_Result::OKAY){ //Calibrate
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SHAL_UART2.sendString("Calibration failed");
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return SHAL_Result::ERROR;
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}
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if(enable() != SHAL_Result::OKAY){
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SHAL_UART2.sendString("Could not enable from init\r\n");
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return SHAL_Result::ERROR;
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}
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configureAlignment(SHAL_ADC_Alignment::RIGHT);
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configureResolution(SHAL_ADC_Resolution::B12);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::calibrate() {
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SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
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if(disable() != SHAL_Result::OKAY){
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return SHAL_Result::ERROR;
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}
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SHAL_delay_us(1000);
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if ((*control_reg.reg & (control_reg.enable_mask | control_reg.disable_mask)) != 0) {
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return SHAL_Result::ERROR;
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}
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SHAL_clear_bitmask(control_reg.reg, control_reg.differential_mode_mask);
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SHAL_apply_bitmask(control_reg.reg, control_reg.calibration_mask);
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if ((*control_reg.reg & control_reg.calibration_mask) == 0) {
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return SHAL_Result::ERROR;
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}
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if (!SHAL_WAIT_FOR_CONDITION_US(((*control_reg.reg & control_reg.calibration_mask) != 0),500)) { //Wait for conversion
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return SHAL_Result::ERROR; //Failed sequence
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}
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SHAL_UART2.sendString("Calibration OK\r\n");
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return SHAL_Result::OKAY;
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}
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uint16_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time) {
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auto data_reg = getADCDataReg(m_ADCKey); //Where our output will be stored
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auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey,channel);
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SHAL_set_bits(sampleTimeReg.reg,3,static_cast<uint8_t>(time),sampleTimeReg.channel_offset); //Set sample time register TODO un-hardcode bit width?
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addADCChannelToSequence(channel,0); //Use index 0 to convert channel
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if(setADCSequenceAmount(1) == SHAL_Result::ERROR){return 0;} //Since we're using single convert, convert 1 channel
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if(enable() != SHAL_Result::OKAY){
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return 0;
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}
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startConversion(); //Start ADC conversion
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auto ISR_reg = getADCISRReg(m_ADCKey);
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if(!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_sequence_mask) != 0),500)){ //Wait for conversion
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return 0; //Failed
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}
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return *data_reg.reg;
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}
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SHAL_Result SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, const int numChannels, uint16_t* result, SHAL_ADC_SampleTime time) {
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auto data_reg = getADCDataReg(m_ADCKey); //Where our output will be stored
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setADCSequenceAmount(numChannels); //Convert the correct amount of channels
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for(int i = 0; i < numChannels; i++){
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auto channel = channels[i];
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auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey,channel);
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SHAL_set_bits(sampleTimeReg.reg,3,static_cast<uint8_t>(time),sampleTimeReg.channel_offset); //Set sample time register TODO un-hardcode bit width?
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addADCChannelToSequence(channel,i); //Use index 0 to convert channel
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}
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startConversion(); //Start ADC conversion
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auto ISR_reg = getADCISRReg(m_ADCKey);
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for(int i = 0; i < numChannels; i++) {
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if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_conversion_mask) != 0),500)) { //Wait for conversion
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return SHAL_Result::ERROR; //Failed conversion
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}
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result[i] = *data_reg.reg;
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}
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if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_sequence_mask) != 0),500)) { //Wait for conversion
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return SHAL_Result::ERROR; //Failed sequence
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}
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::enable() {
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if(!isValid()){
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SHAL_UART2.sendString("Enable failed: Invalid \r\n");
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return SHAL_Result::ERROR;
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}
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SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
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SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
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if(!SHAL_WAIT_FOR_CONDITION_MS((*control_reg.reg & control_reg.calibration_mask) == 0, 100)) {
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return SHAL_Result::ERROR;
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}
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if (*control_reg.reg & control_reg.enable_mask) {
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return SHAL_Result::OKAY; //Not an error
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}
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if (*control_reg.reg & control_reg.disable_mask) {
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return SHAL_Result::ERROR;
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}
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//Clear ADRDY flag by writing 1 to it
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SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask);
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//Enable the ADC by setting ADEN
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SHAL_apply_bitmask(control_reg.reg, control_reg.enable_mask);
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if(!SHAL_WAIT_FOR_CONDITION_MS((*ISR_reg.reg & ISR_reg.ready_mask) != 0, 100)) {
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return SHAL_Result::ERROR;
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}
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//Clear ADRDY again
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SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::wakeFromDeepSleep() {
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SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey); //ADC Control register
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SHAL_clear_bitmask(control_reg.reg,control_reg.deep_power_down_mask); //Wake ADC from sleep
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SHAL_apply_bitmask(control_reg.reg,control_reg.voltage_regulator_mask);
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SHAL_delay_us(50); //Wait for regulator to stabilize
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::disable() {
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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auto control_reg = getADCControlReg(m_ADCKey);
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//Stop any ongoing conversion
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if (*control_reg.reg & control_reg.start_mask) {
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SHAL_apply_bitmask(control_reg.reg, control_reg.stop_mask);
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}
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//Only disable if ADC is enabled otherwise it hangs
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if (*control_reg.reg & control_reg.enable_mask) {
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SHAL_apply_bitmask(control_reg.reg, control_reg.disable_mask);
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if (!SHAL_WAIT_FOR_CONDITION_MS(((*control_reg.reg & (control_reg.enable_mask | control_reg.disable_mask)) == 0),500)){
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return SHAL_Result::ERROR;
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}
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}
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::startConversion() {
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auto control_reg = getADCControlReg(m_ADCKey);
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SHAL_apply_bitmask(control_reg.reg,control_reg.start_mask);
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return SHAL_Result::OKAY;
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}
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bool SHAL_ADC::isValid() {
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if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
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return false;
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}
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return true;
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}
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SHAL_Result SHAL_ADC::configureResolution(SHAL_ADC_Resolution resolution) {
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
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SHAL_set_bits(config_reg.reg,2,static_cast<uint8_t>(resolution),config_reg.resolution_offset);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::configureAlignment(SHAL_ADC_Alignment alignment) {
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if(!isValid()){
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return SHAL_Result::ERROR;
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}
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SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
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//TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
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SHAL_set_bits(config_reg.reg,1,static_cast<uint8_t>(alignment),config_reg.alignment_offset);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::setADCSequenceAmount(uint32_t amount) {
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if(!isValid()){return SHAL_Result::ERROR;}
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if(amount == 0){
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return SHAL_Result::ERROR;
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}
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SHAL_ADC_Sequence_Amount_Reg sequence_amount_reg = getADCSequenceAmountRegister(m_ADCKey);
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SHAL_set_bits(sequence_amount_reg.reg, 4, amount - 1, sequence_amount_reg.offset);
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return SHAL_Result::OKAY;
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}
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SHAL_Result SHAL_ADC::addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t index) {
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if(!isValid()){return SHAL_Result::ERROR;}
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auto sequenceRegisters = getADCSequenceRegisters(m_ADCKey);
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auto channelNum = static_cast<uint8_t>(channel);
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uint32_t bitSection = (index + 1) % 5; //Need a new variable since SQR1 has its data bits shifted up by one section to make room for the L section
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uint32_t sequenceRegNumber = (index + 1) / 5;
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volatile uint32_t* sequenceReg = sequenceRegisters.regs[sequenceRegNumber];
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uint32_t bitSectionOffset = sequenceRegisters.offsets[bitSection];
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if(sequenceRegNumber != 0){
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*sequenceReg = 0; //Clear previous conversions
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}
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else{
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*sequenceReg &= 0x0000000F;
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}
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SHAL_set_bits(sequenceReg,5,channelNum,bitSectionOffset);
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return SHAL_Result::OKAY;
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}
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SHAL_ADC &ADCManager::get(ADC_Key key) {
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return m_ADCs[static_cast<uint8_t>(key)];
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}
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SHAL_ADC& ADCManager::getByIndex(int index) {
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if(index < static_cast<int>(ADC_Key::NUM_ADC)){
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return m_ADCs[index];
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}
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return m_ADCs[0];
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} |