106 lines
3.6 KiB
C++
106 lines
3.6 KiB
C++
/**
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******************************************************************************
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* @file SHAL_TIM_REG.h
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* @author Luca Lizaranzu
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* @brief Defines universal macros and objects used across all STM32 families
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******************************************************************************
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*/
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#ifndef SHAL_TIM_REG_H
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#define SHAL_TIM_REG_H
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#include <cassert>
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#include <stm32f072xb.h>
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#include "SHAL_CORE.h"
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#include "SHAL_TIM_TYPES.h"
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enum class Timer_Key : uint8_t { //For STM32F072
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S_TIM1,
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S_TIM2,
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S_TIM3,
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S_TIM6,
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S_TIM7,
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S_TIM14,
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S_TIM15,
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S_TIM16,
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S_TIM17,
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NUM_TIMERS,
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S_TIM_INVALID
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};
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#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
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#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
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#define SHAL_TIM3 TimerManager::get(Timer_Key::S_TIM3)
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#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
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#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
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#define SHAL_TIM14 TimerManager::get(Timer_Key::S_TIM14)
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#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
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#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
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#define SHAL_TIM17 TimerManager::get(Timer_Key::S_TIM17)
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//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
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constexpr TIM_RCC_Enable getTimerRCC(Timer_Key t) {
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switch(t) {
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case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_Pos};
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case Timer_Key::S_TIM2: return {&RCC->APB1ENR, RCC_APB1ENR_TIM2EN_Pos};
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case Timer_Key::S_TIM3: return {&RCC->APB1ENR, RCC_APB1ENR_TIM3EN_Pos};
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case Timer_Key::S_TIM6: return {&RCC->APB1ENR, RCC_APB1ENR_TIM6EN_Pos};
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case Timer_Key::S_TIM7: return {&RCC->APB1ENR, RCC_APB1ENR_TIM7EN_Pos};
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case Timer_Key::S_TIM14: return {&RCC->APB1ENR, RCC_APB1ENR_TIM14EN_Pos};
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case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN_Pos};
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case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN_Pos};
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case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN_Pos};
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case Timer_Key::NUM_TIMERS:
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case Timer_Key::S_TIM_INVALID:
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assert(false);
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return {nullptr, 0};; //Unreachable
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}
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__builtin_unreachable();
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}
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//Get actual register value based on enum
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constexpr volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
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switch(t) {
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case Timer_Key::S_TIM1: return TIM1;
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case Timer_Key::S_TIM2: return TIM2;
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case Timer_Key::S_TIM3: return TIM3;
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case Timer_Key::S_TIM6: return TIM6;
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case Timer_Key::S_TIM7: return TIM7;
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case Timer_Key::S_TIM14: return TIM14;
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case Timer_Key::S_TIM15: return TIM15;
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case Timer_Key::S_TIM16: return TIM16;
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case Timer_Key::S_TIM17: return TIM17;
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case Timer_Key::NUM_TIMERS:
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case Timer_Key::S_TIM_INVALID:
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assert(false);
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return nullptr; //Unreachable
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}
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__builtin_unreachable();
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}
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constexpr IRQn_Type getIRQn(Timer_Key t) {
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switch(t) {
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case Timer_Key::S_TIM1: return TIM1_BRK_UP_TRG_COM_IRQn;
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case Timer_Key::S_TIM2: return TIM2_IRQn;
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case Timer_Key::S_TIM3: return TIM3_IRQn;
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case Timer_Key::S_TIM6: return TIM6_DAC_IRQn;
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case Timer_Key::S_TIM7: return TIM7_IRQn;
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case Timer_Key::S_TIM14: return TIM14_IRQn;
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case Timer_Key::S_TIM15: return TIM15_IRQn;
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case Timer_Key::S_TIM16: return TIM16_IRQn;
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case Timer_Key::S_TIM17: return TIM17_IRQn;
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case Timer_Key::NUM_TIMERS:
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case Timer_Key::S_TIM_INVALID:
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assert(false);
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return TIM1_BRK_UP_TRG_COM_IRQn; //Unreachable
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}
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__builtin_unreachable();
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}
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#endif |