Continuing ADC port
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@@ -70,9 +70,7 @@ SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
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}
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SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
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constexpr uint32_t ADCSEL_MASK = RCC_CCIPR_ADCSEL_Msk; // covers bits 29:28
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SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, ADCSEL_MASK, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
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SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Msk, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
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switch(clockSource){
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case ADC_Clock_Source::SHAL_PLLSAI1:
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@@ -84,10 +82,28 @@ SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
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case ADC_Clock_Source::SHAL_MSI:
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break; //TODO implement this
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}
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return res;
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}
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SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
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volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
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volatile uint32_t* SMPReg = nullptr;
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uint32_t pos = 0;
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auto channelNum = static_cast<uint8_t>(channel);
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if (channelNum <= 9) {
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SMPReg = &ADCReg->SQR1;
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pos = (channelNum * 3);
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} else {
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SMPReg = &ADCReg->SQR2;
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pos = ((channelNum - 10) * 3);
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}
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return {SMPReg, pos};
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}
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constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
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switch(key){
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case ADC_Key::S_ADC1:
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