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Finished ADC, updating timer code

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This commit is contained in:
Ea-r-th
2025-10-17 00:59:12 -07:00
parent af21480aff
commit 6c8fa459f8
14 changed files with 267 additions and 164 deletions
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4
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_F072xB.h
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@@ -6,8 +6,8 @@
******************************************************************************
*/
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#ifndef SHAL_TIM_REG_F072XB_H
#define SHAL_TIM_REG_F072XB_H
#include <cassert>
#include <stm32f072xb.h>

122
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_L432KC.h Normal file
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@@ -0,0 +1,122 @@
/**
******************************************************************************
* @file SHAL_TIM_REG.h
* @author Luca Lizaranzu
* @brief Defines universal macros and objects used across all STM32 families
******************************************************************************
*/
#ifndef SHAL_TIM_REG_L432KC_H
#define SHAL_TIM_REG_L432KC_H
#include <cassert>
#include <stm32l432xx.h>
#include "SHAL_CORE.h"
#include "SHAL_TIM_TYPES.h"
enum class Timer_Key : uint8_t { //For STM32L432
S_TIM1,
S_TIM2,
S_TIM6,
S_TIM7,
S_TIM15,
S_TIM16,
NUM_TIMERS,
S_TIM_INVALID
};
//Lookup table for timer typedefs
static volatile TIM_TypeDef* TIM_TABLE[6] = {
TIM1,
TIM2,
TIM6,
TIM7,
TIM15,
TIM16,
};
#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
static inline SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->SR;
return res;
}
static inline SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk, TIM_CR1_UDIS, TIM_CR1_OPM, TIM_CR1_CMS_Pos};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
static inline SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
static inline SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
static inline SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_Pos};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN_Pos};
case Timer_Key::S_TIM6: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN_Pos};
case Timer_Key::S_TIM7: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN_Pos};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN_Pos};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN_Pos};
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
}
__builtin_unreachable();
}
static inline IRQn_Type getTimerIRQn(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return TIM1_TRG_COM_IRQn;
case Timer_Key::S_TIM2: return TIM2_IRQn;
case Timer_Key::S_TIM6: return TIM6_DAC_IRQn;
case Timer_Key::S_TIM7: return TIM7_IRQn;
case Timer_Key::S_TIM15: return TIM1_BRK_TIM15_IRQn;
case Timer_Key::S_TIM16: return TIM1_UP_TIM16_IRQn;
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
__builtin_unreachable();
}
__builtin_unreachable();
}
#endif

8
SHAL/Include/Peripheral/Timer/SHAL_TIM.h
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@@ -9,7 +9,7 @@
#ifndef SHAL_TIM_H
#define SHAL_TIM_H
#include "SHAL_TIM_REG_F072xB.h"
#include "SHAL_TIM_REG.h"
#include "SHAL_TIM_CALLBACK.h"
#include <array>
@@ -18,7 +18,7 @@ class Timer {
friend class TimerManager;
public:
///
/// Initializes a timer
/// \param prescaler The amount of times the base clock has to cycle before the timer adds one to the count
/// \param autoReload The number of timer counts before the count is reset and IRQ is called
void init(uint32_t prescaler, uint32_t autoReload);
@@ -40,7 +40,7 @@ public:
//Set TIMER_KEY IRQ callback function
void setCallbackFunc(TimerCallback callback){
registerTimerCallback(TIMER_KEY, callback);
registerTimerCallback(m_key, callback);
}
private:
@@ -48,7 +48,7 @@ private:
explicit Timer(Timer_Key t);
Timer();
Timer_Key TIMER_KEY;
Timer_Key m_key;
};

8
SHAL/Include/Peripheral/Timer/SHAL_TIM_REG.h
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@@ -2,8 +2,8 @@
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_REG_H
#define SHMINGO_HAL_SHAL_TIM_REG_H
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
@@ -46,7 +46,7 @@
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#include "SHAL_TIM_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
@@ -92,4 +92,4 @@
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_TIM_REG_H
#endif //SHAL_TIM_REG_H

31
SHAL/Include/Peripheral/Timer/SHAL_TIM_TYPES.h
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@@ -2,14 +2,37 @@
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_TYPES_H
#define SHMINGO_HAL_SHAL_TIM_TYPES_H
#ifndef SHAL_TIM_TYPES_H
#define SHAL_TIM_TYPES_H
#include "SHAL_CORE.h"
struct TIM_RCC_Enable{
volatile uint32_t* busEnableReg;
struct SHAL_TIM_RCC_Register{
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_TIM_Control_Register_1 {
volatile uint32_t* reg;
uint32_t counter_enable_mask;
uint32_t update_disable_mask;
uint32_t one_pulse_mode_mask;
uint32_t center_align_mode_offset;
};
struct SHAL_TIM_DMA_Interrupt_Enable_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_enable_mask;
};
struct SHAL_TIM_Status_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_flag_mask;
};
struct SHAL_TIM_Event_Generation_Register {
volatile uint32_t* reg;
uint32_t update_generation_mask;
};
#endif //SHMINGO_HAL_SHAL_TIM_TYPES_H