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base: lucalizaranzu:3561879c2484696c504e5991bf4bd514f1bafa5e
Branches Tags
lucalizaranzu:main lucalizaranzu:dev lucalizaranzu:button lucalizaranzu:I2C lucalizaranzu:gpio
...
compare: lucalizaranzu:dev
Branches Tags
lucalizaranzu:dev lucalizaranzu:main lucalizaranzu:button lucalizaranzu:I2C lucalizaranzu:gpio

25 Commits
3561879c24 ... dev

Author SHA1 Message Date
Luca Lizaranzu
034361faa8 test 2026-04-02 14:09:53 -07:00
Luca Lizaranzu
36f5b37b5a H7 working 2026-04-01 14:11:41 -07:00
Luca Lizaranzu
1b29371fff Test program done 2026-03-20 11:41:44 -07:00
Luca Lizaranzu
303a554595 uart working but fix send char 2026-03-16 17:10:48 -07:00
Ea-r-th
0b531b10d7 marginal moves towards h7 working 2026-03-13 00:50:15 -07:00
Luca Lizaranzu
ae965d747c Broken H7 Implementation 2026-03-12 16:33:16 -07:00
Ea-r-th
5b0819a300 Timer test 2026-03-11 00:31:40 -07:00
Ea-r-th
43bdee4406 Refactored timer for F0 2026-03-06 21:12:09 -08:00
Luca
3593d8cbd2 Working 2025-11-14 09:37:35 -08:00
Ea-r-th
7a9cd2f70e Ensuring up to date 2025-11-12 15:26:16 -08:00
Ea-r-th
ec0fea608b Finish project 2025-11-11 19:51:21 -08:00
Ea-r-th
b50e7c25f6 Finish testing stage 2025-11-07 00:20:43 -08:00
Ea-r-th
7a24078e18 Most functionality for seat working 2025-11-06 19:58:38 -08:00
Ea-r-th
63fab62727 For sensor project 2025-11-06 02:40:54 -08:00
Ea-r-th
a1458de235 Fixed PWM mode 2025-11-06 00:41:46 -08:00
Ea-r-th
12aedf1ff9 Abstracted registers for PWM and other timer modes 2025-11-05 18:15:32 -08:00
Ea-r-th
aa7a041946 Updated GPIO to new format 2025-11-03 23:17:55 -08:00
Ea-r-th
0b4a6ef584 Known working minimized setup 2025-10-23 20:52:04 -07:00
Ea-r-th
e41cf30c87 Fixed ADC functionality 2025-10-19 18:33:18 -07:00
Ea-r-th
2c5592c2d3 Refactors for L432KC done for all peripherals except GPIO 2025-10-19 01:49:13 -07:00
Ea-r-th
e822b8d9ec Issue: cannot read core 2025-10-17 12:50:16 -07:00
Ea-r-th
04f79cc543 Finished UART refactor 2025-10-17 02:23:56 -07:00
Ea-r-th
d846897296 Finished timer refactor 2025-10-17 01:16:11 -07:00
Ea-r-th
6c8fa459f8 Finished ADC, updating timer code 2025-10-17 00:59:12 -07:00
Ea-r-th
af21480aff ADC sequence abstracted 2025-10-16 21:34:01 -07:00
80 changed files with 34834 additions and 1356 deletions
Expand all files Collapse all files

51
CMakeLists.txt
View File

@@ -1,17 +1,22 @@
cmake_minimum_required(VERSION 3.19)
set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/gcc-arm-none-eabi.cmake)
project(shmingo-HAL)
set(PROJECT_DIR ${CMAKE_CURRENT_SOURCE_DIR})
set(MCU_FAMILY "STM32L4xx" CACHE STRING "MCU family")
set(MCU_MODEL "STM32L432xx" CACHE STRING "MCU model")
enable_language(C ASM CXX)
set(MCU_FAMILY "STM32F0xx")
set(MCU_MODEL "STM32F072xB")
set(CPU_PARAMETERS
-mcpu=cortex-m0
-mthumb)
)
set(STARTUP_SCRIPT MX/L432KC/startup_stm32l432kcux.s)
set(MCU_LINKER_SCRIPT MX/L432KC/STM32L432KCUX_FLASH.ld)
set(STARTUP_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/F030x6/startup_stm32f030x6.S
SHAL/Src/User_Config.h)
set(MCU_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/F030x6/STM32F030XX_FLASH.ld)
set(EXECUTABLE ${CMAKE_PROJECT_NAME})
enable_language(C CXX ASM)
@@ -29,28 +34,35 @@ set(MX_INCLUDE_DIRECTORIES
set(PROJECT_INCLUDE_DIRECTORIES
${CMAKE_CURRENT_SOURCE_DIR}
SHAL/Include/Core/
SHAL/Include/Peripheral/Timer
SHAL/Include/Peripheral/Timer/Reg
SHAL/Include/Peripheral/GPIO
SHAL/Include/Peripheral/GPIO/Reg
SHAL/Include/Peripheral/UART
SHAL/Include/Peripheral/UART/Reg
#[[
SHAL/Include/Peripheral/I2C
SHAL/Include/Peripheral/I2C/Reg
SHAL/Include/Peripheral/ADC
SHAL/Include/Peripheral/ADC/Reg
SHAL/Include/Peripheral/EXT/
SHAL/Include/Peripheral/EXT
SHAL/Include/Peripheral/EXT/Reg
]]#
SHAL/Include/Core/
SHAL/Include/Peripheral/GPIO
SHAL/Include/Peripheral/GPIO/Reg
SHAL/Include/Peripheral/Timer
SHAL/Include/Peripheral/Timer/Reg
SHAL/Src
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include
)
file(GLOB_RECURSE PROJECT_SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/${MCU_FAMILY}/*.c
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/${MCU_FAMILY}/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/Universal/*.c
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/Universal/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/Universal/*.c
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/${MCU_FAMILY}/*.c
#${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/${MCU_FAMILY}/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/main.cpp
#Temporary manual method of including source files to avoid including broken code
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/${MCU_FAMILY}/Peripheral/GPIO/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/${MCU_FAMILY}/Peripheral/Timer/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Src/${MCU_FAMILY}/Core/*.cpp
)
add_executable(${EXECUTABLE}
@@ -59,7 +71,9 @@ add_executable(${EXECUTABLE}
)
target_compile_definitions(${EXECUTABLE} PRIVATE
USE_PWR_LDO_SUPPLY
${MCU_MODEL}
${MCU_FAMILY}
)
target_include_directories(${EXECUTABLE} PRIVATE
@@ -73,6 +87,7 @@ target_compile_options(${EXECUTABLE} PRIVATE
-Wextra
-Wpedantic
-Wno-unused-parameter
-Wno-unused-function
$<$<COMPILE_LANGUAGE:CXX>:
-Wno-volatile
-Wsuggest-override>

26969
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h Normal file
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File diff suppressed because it is too large Load Diff

302
Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h Normal file
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@@ -0,0 +1,302 @@
/**
******************************************************************************
* @file stm32h7xx.h
* @author MCD Application Team
* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32H7xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx
* @{
*/
#ifndef STM32H7xx_H
#define STM32H7xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32H7)
#define STM32H7
#endif /* STM32H7 */
/* Uncomment the line below according to the target STM32H7 device used in your
application
*/
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
!defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
!defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
/* #define STM32H747xG */ /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
/* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
/* #define STM32H7B0xx */ /*!< STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx Devices */
/* #define STM32H7B0xxQ */ /*!< STM32H7B0ABIxQ, STM32H7B0IBKxQ Devices */
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
/* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
/* #define STM32H735xx */ /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */
/* #define STM32H733xx */ /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */
/* #define STM32H730xx */ /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */
/* #define STM32H730xxQ */ /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */
/* #define STM32H725xx */ /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices */
/* #define STM32H723xx */ /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
#error "Dual core device, please select CORE_CM4 or CORE_CM7"
#endif
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.10.6
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
|(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32H743xx)
#include "stm32h743xx.h"
#elif defined(STM32H753xx)
#include "stm32h753xx.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H745xG)
#include "stm32h745xg.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H747xG)
#include "stm32h747xg.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#else
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32h7xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32H7xx_H */
/**
* @}
*/
/**
* @}
*/

104
Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h Normal file
View File

@@ -0,0 +1,104 @@
/**
******************************************************************************
* @file system_stm32h7xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef SYSTEM_STM32H7XX_H
#define SYSTEM_STM32H7XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32H7xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void ExitRun0Mode(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_STM32H7XX_H */
/**
* @}
*/
/**
* @}
*/

6
Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h
View File

@@ -45,8 +45,8 @@
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
#define __MPU_PRESENT 1U /*!< STM32L4xx provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32L4xx uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
@@ -59,7 +59,7 @@
*/
/**
* @brief STM32L4XX Interrupt Number Definition, according to the selected device
* @brief STM32L4xx Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum

249
MX/F030x6/STM32F030XX_FLASH.ld Normal file
View File

@@ -0,0 +1,249 @@
/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : STM32CubeMX
**
** Abstract : Linker script for STM32F030K6Tx series
** 32Kbytes FLASH and 4Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2025 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 4K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 32K
}
/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
} >FLASH
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
. = ALIGN(4);
} >FLASH
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
*(.RamFunc) /* .RamFunc sections */
*(.RamFunc*) /* .RamFunc* sections */
. = ALIGN(4);
} >RAM AT> FLASH
/* Initialized TLS data section */
.tdata : ALIGN(4)
{
*(.tdata .tdata.* .gnu.linkonce.td.*)
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
PROVIDE(__data_end = .);
PROVIDE(__tdata_end = .);
} >RAM AT> FLASH
PROVIDE( __tdata_start = ADDR(.tdata) );
PROVIDE( __tdata_size = __tdata_end - __tdata_start );
PROVIDE( __data_start = ADDR(.data) );
PROVIDE( __data_size = __data_end - __data_start );
PROVIDE( __tdata_source = LOADADDR(.tdata) );
PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source );
PROVIDE( __data_source = LOADADDR(.data) );
PROVIDE( __data_source_end = __tdata_source_end );
PROVIDE( __data_source_size = __data_source_end - __data_source );
/* Uninitialized data section */
.tbss (NOLOAD) : ALIGN(4)
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.tbss .tbss.*)
. = ALIGN(4);
PROVIDE( __tbss_end = . );
} >RAM
PROVIDE( __tbss_start = ADDR(.tbss) );
PROVIDE( __tbss_size = __tbss_end - __tbss_start );
PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
PROVIDE( __tls_base = __tdata_start );
PROVIDE( __tls_end = __tbss_end );
PROVIDE( __tls_size = __tls_end - __tls_base );
PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) );
PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
.bss (NOLOAD) : ALIGN(4)
{
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
PROVIDE( __bss_end = .);
} >RAM
PROVIDE( __non_tls_bss_start = ADDR(.bss) );
PROVIDE( __bss_start = __tbss_start );
PROVIDE( __bss_size = __bss_end - __bss_start );
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack (NOLOAD) :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a:* ( * )
libm.a:* ( * )
libgcc.a:* ( * )
}
}

258
MX/F030x6/startup_stm32f030x6.s Normal file
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/**
******************************************************************************
* @file startup_stm32f030x6.s
* @author MCD Application Team
* @brief STM32F030x4/STM32F030x6 devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word 0 /* Reserved */
.word RTC_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* Reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
.word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word 0 /* Reserved */
.word TIM3_IRQHandler /* TIM3 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word TIM14_IRQHandler /* TIM14 */
.word 0 /* Reserved */
.word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */
.word 0 /* Reserved */
.word SPI1_IRQHandler /* SPI1 */
.word 0 /* Reserved */
.word USART1_IRQHandler /* USART1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler

755
MX/H753ZIT6/startup_stm32h753xx.s Normal file
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@@ -0,0 +1,755 @@
/**
******************************************************************************
* @file startup_stm32h753xx.s
* @author MCD Application Team
* @brief STM32H753xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Call the ExitRun0Mode function to configure the power supply */
bl ExitRun0Mode
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word CRYP_IRQHandler /* Crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler

192
MX/H753ZIT6/stm32h753zitx_flash.ld Normal file
View File

@@ -0,0 +1,192 @@
/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : STM32CubeMX
**
** Abstract : Linker script for STM32H753ZITx series
** 2048Kbytes FLASH and 1056Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >DTCMRAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >DTCMRAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >DTCMRAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
}

4
Makefile
View File

@@ -6,8 +6,8 @@ BUILD_TYPE ?= Debug
TOOLCHAIN := gcc-arm-none-eabi.cmake
# MCU target (override on command line: make build MCU_MODEL=STM32F051x8)
MCU_MODEL ?= STM32L432xx
MCU_FAMILY ?= STM32L4xx
MCU_MODEL ?= STM32F072xB
MCU_FAMILY ?= STM32F0xx
# --- Default target ---
all: build

10
README.md
View File

@@ -1,3 +1,9 @@
# Shmingo-HAL
Instructions to run
A custom HAL for STM32F0 MCUs
A binary is provided (Shmingo-HAL, formats are bin,hex,elf)
Download STM32CubeProgrammer
point to the binary file
Program via SWD (on Nucleo devices, you can just plug into USB and connect via onboard USB to SWD adapter)
You can also use an external ST-Link to program with the dedicated SWD pins

132
SHAL/Include/Core/SHAL_CORE.h
View File

@@ -10,6 +10,7 @@
#define SHMINGO_HAL_SHAL_CORE_H
#include <cstdint>
#include <cstddef>
//Overall init function for SHAL --------------------------
@@ -41,8 +42,13 @@ enum class SHAL_Result{
//Currently configures systick to count down in microseconds
inline uint32_t ticks = 0;
void systick_init();
extern "C" void SysTick_Handler();
static uint32_t millis();
//Max of 16ms, use SHAL_delay_ms for longer delay
void SHAL_delay_us(uint32_t us);
@@ -70,16 +76,78 @@ bool SHAL_wait_for_condition_ms(Condition cond, uint32_t timeout_ms) {
return false; // timeout
}
void SHAL_set_bits(volatile uint32_t* reg, uint32_t size, uint32_t bits, uint32_t offset){
uint32_t mask = (1 << (size)) - 1;
*reg &= ~(mask << offset);
*reg |= bits << offset;
}
bool SHAL_check_bit(const volatile uint32_t* reg, uint32_t mask);
void SHAL_apply_bitmask(volatile uint32_t* reg, uint32_t mask){
*reg &= ~(mask);
*reg |= mask;
}
bool SHAL_wait_for_bit_set_us(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
bool SHAL_wait_for_bit_clear_us(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
bool SHAL_wait_for_bit_set_ms(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
bool SHAL_wait_for_bit_clear_ms(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
#define SHAL_set_bits(reg, size, bits, offset) \
do { \
if ((reg) != NULL) { \
uint32_t _mask = (size == 32) ? 0xFFFFFFFFU : ((1U << (size)) - 1U); \
*(reg) &= ~((uint32_t)(_mask) << (offset)); \
*(reg) |= ((uint32_t)(bits) << (offset)); \
} \
} while (0)
#define SHAL_flip_bits(reg, size, offset) \
do { \
if ((reg) != NULL) { \
uint32_t _mask = ((1U << (size)) - 1U); \
*(reg) ^= (_mask << (offset)); \
} \
} while (0)
#define SHAL_set_bits_16(reg, size, bits, offset) \
do { \
if ((reg) != NULL) { \
uint16_t _mask = (uint16_t)((1U << (size)) - 1U); \
*(reg) &= (uint16_t)~((uint16_t)(_mask) << (offset)); \
*(reg) |= (uint16_t)((uint16_t)(bits) << (offset)); \
} \
} while (0)
#define SHAL_clear_bitmask(reg, mask) \
do { \
*(reg) &= ~(mask); \
} while (0)
#define SHAL_apply_bitmask(reg, mask) \
do { \
SHAL_clear_bitmask((reg), (mask)); \
*(reg) |= (mask); \
} while (0)
#define SHAL_clear_register_value(reg) \
do { \
if ((reg) != NULL) { \
*(reg) = 0; \
} \
} while (0)
#define SHAL_set_register_value(reg, value) \
do { \
if ((reg) != NULL) { \
*(reg) = (uint32_t)(value); \
} \
} while (0)
#define SHAL_set_register_value_16(reg, value) \
do { \
if ((reg) != NULL) { \
*(reg) = (uint16_t)(value); \
} \
} while (0)
void SHAL_print_register(const volatile uint32_t* reg);
//---------------------------------------------------------
@@ -165,6 +233,52 @@ void SHAL_apply_bitmask(volatile uint32_t* reg, uint32_t mask){
#elif defined(STM32L4S9xx)
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32H753ZIT6)
#include "SHAL_TIM_REG_H753xx.h"
#elif defined(STM32H743xx)
#include "stm32h743xx.h"
#elif defined(STM32H753xx)
#include "stm32h753xx.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H745xG)
#include "stm32h745xg.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H747xG)
#include "stm32h747xg.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#else
#error "Please select first the target STM32 device used in your application (in stm32f0xx.h file)"
#endif

24
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_F072xB.h
View File

@@ -8,6 +8,30 @@
#include "SHAL_CORE.h"
#include "SHAL_ADC_TYPES.h"
enum class SHAL_ADC_Channel : uint32_t { //TODO remove unused or non existing channels?
CH0 = 0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
CH8,
CH9,
CH10,
CH11,
CH12,
CH13,
CH14,
CH15,
CH16,
CHTemp,
CHRef,
CHBat,
NO_ADC_MAPPING
};
#define SHAL_ADC1 SHAL_ADC(1)
enum class ADC_Key : uint8_t{

213
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_H753ZI.h Normal file
View File

@@ -0,0 +1,213 @@
//
// Created by Luca on 10/8/2025.
//
#ifndef SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H
#define SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H
#include "SHAL_CORE.h"
#include "SHAL_ADC_TYPES.h"
#include "stm32h753xx.h"
#define SHAL_ADC1 SHAL_ADC(1)
#define SHAL_ADC2 SHAL_ADC(2)
#define SHAL_ADC3 SHAL_ADC(3)
#define NUM_ADCS 3
#define NUM_ADC_CHANNELS 16
enum class SHAL_ADC_Channel : uint32_t {
CH0 = 0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
CH8,
CH9,
CH10,
CH11,
CH12,
CH13,
CH14,
CH15,
CH16,
CH17,
CH18,
CHTemp,
CHRef,
CHBat,
NO_ADC_MAPPING
};
enum class ADC_Key : uint8_t{
S_ADC1 = 0,
S_ADC2 = 1,
S_ADC3 = 2,
NUM_ADC = 3,
INVALID = 255
};
enum class SHAL_ADC_Resolution : uint8_t { //TODO figure out what to do with this difference
B16 = 0x00,
B14 = 0x01,
B12 = 0x02,
B10 = 0x03,
B8 = 0x04,
B6 = 0x05,
};
enum class SHAL_ADC_Clock_Mode {
ASYNC = 0x00,
SYNC_BY_1 = 0x01,
SYNC_BY_2 = 0x02,
SYNC_BY_4 = 0x03,
};
static volatile ADC_TypeDef* ADC_TABLE[3] = { //Lookup table for ADCs
ADC1,
ADC2,
ADC3,
};
static volatile ADC_Common_TypeDef* ADC_CCR_TABLE[3] = { //Common registers
ADC12_COMMON, //1 and 2 share a common register
ADC12_COMMON,
ADC3_COMMON,
};
enum class ADC_Clock_Source : uint32_t {
SHAL_NO_CLOCK = 0x00,
SHAL_PLLSAI1 = 0x01,
SHAL_PLLSYS = 0x02,
SHAL_SYSCLK = 0x03,
};
static SHAL_ADC_Common_Control_Reg getADCCommonControl(ADC_Key key) {
SHAL_ADC_Common_Control_Reg res = {
.reg = nullptr,
.VoltageRefEnable = ADC_CCR_VREFEN,
.TempSensorEnable = ADC_CCR_TSEN,
.VBatteryEnable = ADC_CCR_VBATEN,
.clock_mode_position = ADC_CCR_CKMODE_Pos
};
res.reg = &ADC_CCR_TABLE[static_cast<uint8_t>(key)]->CCR;
return res;
}
static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(const ADC_Key key){
switch (key) {
case ADC_Key::S_ADC1:
case ADC_Key::S_ADC2:
return {&RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN};
case ADC_Key::S_ADC3:
return {&RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN};
default:
__builtin_unreachable();
}
}
static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN,
ADC_CR_ADSTP,
ADC_CR_ADDIS,
ADC_CR_ADCAL,
ADC_CR_ADSTART,
ADC_CR_DEEPPWD,
ADC_CR_ADVREGEN,
ADC_CR_ADCALDIF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
return res;
}
static inline SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
//NOTE offset of 33 means the function is deprecated
SHAL_ADC_Config_Reg res = {nullptr,
ADC_CFGR_CONT,
ADC_CFGR_RES_Pos,
0, //TODO 0 is broken, shouldnt have alignment
ADC_CFGR_CONT_Msk
};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CFGR);
return res;
}
static inline SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
SHAL_ADC_ISR_Reg res = {nullptr,
ADC_ISR_EOC,
ADC_ISR_EOS,
ADC_ISR_ADRDY,
ADC_ISR_OVR,
ADC_ISR_LDORDY};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
return res;
}
static inline SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* SMPReg = nullptr;
uint32_t pos;
auto channelNum = static_cast<uint8_t>(channel);
if (channelNum <= 9) {
SMPReg = &ADCReg->SMPR1;
pos = (channelNum * 3);
} else {
SMPReg = &ADCReg->SMPR2;
pos = ((channelNum - 10) * 3);
}
return {SMPReg, pos};
}
static inline SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
return res;
}
static SHAL_ADC_Sequence_Reg getADCSequenceRegister(ADC_Key key, uint32_t conversionNum){
volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* sqr[4] = {&adc_reg->SQR1,
&adc_reg->SQR2,
&adc_reg->SQR3,
&adc_reg->SQR4,
};
const uint8_t sqrIndex = conversionNum / 5; //CONVERSION NUM STARTS AT 1! AS PER DATASHEET REFERENCING IT AS SQ1
const uint32_t offset = (((conversionNum) % 5) * 6);
return {sqr[sqrIndex], offset};
}
static SHAL_ADC_Preselect_Reg getADCPreselectRegister(ADC_Key key, SHAL_ADC_Channel channel) {
SHAL_ADC_Preselect_Reg res = {nullptr, static_cast<uint32_t>(channel)};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->PCSEL);
return res;
}
#endif //SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H

116
SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_L432KC.h
View File

@@ -11,99 +11,151 @@
#define SHAL_ADC1 SHAL_ADC(1)
#define NUM_ADCS 1
#define NUM_ADC_CHANNELS 16
enum class SHAL_ADC_Channel : uint32_t {
CH0 = 0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
CH8,
CH9,
CH10,
CH11,
CH12,
CH13,
CH14,
CH15,
CH16,
CHTemp,
CHRef,
CHBat,
NO_ADC_MAPPING
};
enum class ADC_Key : uint8_t{
S_ADC1 = 0,
NUM_ADC = 1,
INVALID = 255
};
enum class ADC_Clock_Source : uint8_t {
SHAL_SYSCLK,
SHAL_PLLSAI1,
SHAL_PLL,
SHAL_MSI
enum class ADC_Clock_Source : uint32_t {
SHAL_NO_CLOCK = 0x00,
SHAL_PLLSAI1 = 0x01,
SHAL_PLLSYS = 0x02,
SHAL_SYSCLK = 0x03,
};
static volatile ADC_TypeDef* ADC_TABLE[1] = { //Lookup table for ADCs
ADC1,
};
SHAL_ADC_Common_Control_Reg getADCCommonControl() {
static inline SHAL_ADC_Common_Control_Reg getADCCommonControl() {
return {&ADC1_COMMON->CCR,ADC_CCR_VREFEN,ADC_CCR_TSEN,ADC_CCR_VBATEN};
}
SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
SHAL_ADC_RCC_Enable_Reg res = {nullptr, RCC_AHB2ENR_ADCEN};
static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(ADC_Key key){
SHAL_ADC_RCC_Enable_Reg res = {&RCC->AHB2ENR, RCC_AHB2ENR_ADCEN};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN, ADC_CR_ADDIS, ADC_CR_ADCAL, ADC_CR_ADSTART};
SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN,
ADC_CR_ADSTP,
ADC_CR_ADDIS,
ADC_CR_ADCAL,
ADC_CR_ADSTART,
ADC_CR_DEEPPWD,
ADC_CR_ADVREGEN,
ADC_CR_ADCALDIF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
return res;
}
SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
static inline SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
SHAL_ADC_Config_Reg res = {nullptr, ADC_CFGR_CONT, ADC_CFGR_RES_Pos, ADC_CFGR_ALIGN_Pos};
SHAL_ADC_Config_Reg res = {nullptr, ADC_CFGR_CONT, ADC_CFGR_RES_Pos, ADC_CFGR_ALIGN_Pos, ADC_CFGR_CONT_Msk};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CFGR);
return res;
}
SHAL_ADC_ISR getADCISR(ADC_Key key){
SHAL_ADC_ISR res = {nullptr, ADC_ISR_EOC};
static inline SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
SHAL_ADC_ISR_Reg res = {nullptr, ADC_ISR_EOC, ADC_ISR_EOS, ADC_ISR_ADRDY, ADC_ISR_OVR};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
return res;
}
SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
return res;
}
SHAL_ADC_Clock_Reg getADCClockSelectRegister(ADC_Clock_Source clockSource) {
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Msk, 1U << RCC_CCIPR_ADCSEL_Pos}; //Default to PLLSAI1
static inline SHAL_ADC_Clock_Reg getADCClockSelectRegister() {
SHAL_ADC_Clock_Reg res = {&RCC->CCIPR, RCC_CCIPR_ADCSEL_Pos}; //Position
switch(clockSource){
case ADC_Clock_Source::SHAL_PLLSAI1:
res.mask = 1U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_PLL:
res.mask = 2U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_SYSCLK:
res.mask = 3U << RCC_CCIPR_ADCSEL_Pos;
case ADC_Clock_Source::SHAL_MSI:
break; //TODO implement this
}
return res;
}
SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
static inline SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
volatile uint32_t* SMPReg = nullptr;
uint32_t pos = 0;
uint32_t pos;
auto channelNum = static_cast<uint8_t>(channel);
if (channelNum <= 9) {
SMPReg = &ADCReg->SQR1;
SMPReg = &ADCReg->SMPR1;
pos = (channelNum * 3);
} else {
SMPReg = &ADCReg->SQR2;
SMPReg = &ADCReg->SMPR2;
pos = ((channelNum - 10) * 3);
}
return {SMPReg, pos};
}
static inline SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
return res;
}
static inline SHAL_ADC_Sequence_Reg getADCSequenceRegisters(ADC_Key key){
volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];
SHAL_ADC_Sequence_Reg res = {{&adc_reg->SQR1,
&adc_reg->SQR2,
&adc_reg->SQR3,
&adc_reg->SQR4,
nullptr,
nullptr},
{0,
6,
12,
18,
24}
};
return res;
}
constexpr ADC_TypeDef* getADCRegister(ADC_Key key){
switch(key){
case ADC_Key::S_ADC1:

45
SHAL/Include/Peripheral/ADC/SHAL_ADC.h
View File

@@ -16,26 +16,28 @@ class SHAL_ADC {
public:
SHAL_Result init();
SHAL_Result init(ADC_Key key, SHAL_ADC_Sample_Mode mode);
SHAL_Result calibrate();
SHAL_Result calibrate(SHAL_ADC_Sample_Mode sampleMode) const;
SHAL_Result configureResolution(SHAL_ADC_Resolution resolution);
SHAL_Result configureResolution(SHAL_ADC_Resolution resolution) const;
SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment);
SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment) const;
SHAL_Result preselectChannel(SHAL_ADC_Channel channel) const;
/// Performs analog to digital conversion on a single channel, one time
/// \param channel Channel to be converted
/// \param time ADC_SampleTime - amount of clock cycles per conversion
/// \param time SHAL_ADC_SampleTime - amount of clock cycles per conversion
/// \return resulting value
uint16_t singleConvertSingle(SHAL_ADC_Channel channel, ADC_SampleTime time = ADC_SampleTime::C239);
uint32_t singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8) const;
/// Performs analog to digital conversion on multiple channels, one time
/// \param channels Pointer to an array of channels to convert
/// \param numChannels Number of channels to convert
/// \param result Pointer to store converted channel results in
/// \param time ADC_SampleTime - amount of clock cycles per conversion
void multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, ADC_SampleTime time = ADC_SampleTime::C239);
/// \param time SHAL_ADC_SampleTime - amount of clock cycles per conversion
SHAL_Result multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8);
@@ -45,8 +47,30 @@ private:
ADC_Key m_ADCKey = ADC_Key::INVALID;
bool isValid();
SHAL_Result disable();
//Checks to see if instance is initialized with a proper ADC peripheral tag
bool isValid() const;
//Enabled peripheral
SHAL_Result enable() const;
//Disables peripheral
SHAL_Result disable() const;
//Wake up ADC from initial deep sleep state
SHAL_Result wakeFromDeepSleep() const;
SHAL_Result startConversion() const;
/// Adds an ADC channel to the conversion sequence
/// \param channel Channel to add
/// \param conversionNumber Index to add channel to (ADC channel will be the nth channel to convert
/// \return Result
SHAL_Result addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t conversionNumber) const;
/// Sets the amount of ADC channels to convert
/// \param amount Number of channels to convert
/// \return
SHAL_Result setADCSequenceAmount(uint32_t amount) const;
};
@@ -61,7 +85,6 @@ public:
static SHAL_ADC& getByIndex(int index);
ADCManager() = delete;
private:

44
SHAL/Include/Peripheral/ADC/SHAL_ADC_REG.h
View File

@@ -88,6 +88,50 @@
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#elif defined(STM32H743xx)
#include "stm32h743xx.h"
#elif defined(STM32H753xx)
#include "SHAL_ADC_REG_H753ZI.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H745xG)
#include "stm32h745xg.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H747xG)
#include "stm32h747xg.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

84
SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
View File

@@ -5,84 +5,98 @@
#ifndef SHMINGO_HAL_SHAL_ADC_TYPES_H
#define SHMINGO_HAL_SHAL_ADC_TYPES_H
#include "SHAL_CORE.h"
//Common register among all ADC peripherals
struct SHAL_ADC_Common_Control_Reg {
volatile uint32_t* reg;
uint32_t VoltageRefEnable;
uint32_t TempSensorEnable;
uint32_t VBatteryEnable;
uint32_t clock_mode_position;
};
//Register controlling the ADC peripheral clock
struct SHAL_ADC_RCC_Enable_Reg {
volatile uint32_t* reg;
uint32_t mask;
};
//Register with ADC controls
struct SHAL_ADC_Control_Reg {
volatile uint32_t* reg;
uint32_t enable_mask;
uint32_t stop_mask;
uint32_t disable_mask;
uint32_t calibration_mask;
uint32_t start_mask;
uint32_t deep_power_down_mask;
uint32_t voltage_regulator_mask;
uint32_t sample_mode_offset;
};
//Register controlling ADC configuration
struct SHAL_ADC_Config_Reg {
volatile uint32_t* reg;
uint32_t continue_mask;
uint32_t resolution_offset;
uint32_t alignment_offset;
uint32_t continuous_mode_mask;
};
//Register for all ADC data
struct SHAL_ADC_Data_Reg {
volatile uint32_t* reg;
uint32_t mask;
};
struct SHAL_ADC_ISR {
//Register for the interrupt service routine for ADCs
struct SHAL_ADC_ISR_Reg {
volatile uint32_t* reg;
uint32_t end_of_conversion_mask;
uint32_t end_of_sequence_mask;
uint32_t ready_mask;
uint32_t overrun_mask;
uint32_t ldo_ready_mask;
};
//Register controlling the clock source for the ADC
struct SHAL_ADC_Clock_Reg {
volatile uint32_t* reg;
uint32_t clear;
uint32_t mask;
uint32_t offset;
};
//Register controlling the sampling time of ADC samples
struct SHAL_ADC_Channel_Sampling_Time_Reg {
volatile uint32_t* reg;
uint32_t channel_offset;
};
enum class SHAL_ADC_Channel : uint32_t {
CH0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
CH8,
CH9,
CH10,
CH11,
CH12,
CH13,
CH14,
CH15,
CHTemp,
CHRef,
CHBat
//Register controlling the number of conversions to do in one sequence
struct SHAL_ADC_Sequence_Amount_Reg {
volatile uint32_t* reg;
uint32_t offset;
};
enum class ADC_SampleTime : uint32_t {
C1 = 0x00, //1.5 cycles per sample F0
/*Register group controlling which ADC channels to convert. DO NOT USE THE FOLLOWING ILLEGAL COMBINATIONS:
*reg 1 + offset 1
*Any sections after the last one (for example, max for a 16 channel register is reg 4 offset 2*/
struct SHAL_ADC_Sequence_Reg {
volatile uint32_t* reg;
uint32_t sequence_offset;
};
struct SHAL_ADC_Preselect_Reg {
volatile uint32_t* reg;
uint32_t channel_offset;
};
enum class SHAL_ADC_SampleTime : uint32_t {
C1 = 0x00, //1.5 cycles per sample (F0 only, timings change on other ADC architectures)
C2 = 0x01, //7.5 cycles
C3 = 0x02, //13.5 cycles
C4 = 0x03, //28.5 cycles
@@ -92,16 +106,14 @@ enum class ADC_SampleTime : uint32_t {
C8 = 0x07 //239.5 cycles
};
enum class SHAL_ADC_Resolution : uint8_t {
B12 = 0x00,
B10 = 0x01,
B8 = 0x02,
B6 = 0x03,
};
enum class SHAL_ADC_Alignment : uint8_t {
RIGHT = 0x00,
LEFT = 0x01,
};
enum class SHAL_ADC_Sample_Mode {
SINGLE_ENDED = 0,
DIFFERENTIAL = 1,
};
#endif //SHMINGO_HAL_SHAL_ADC_TYPES_H

25
SHAL/Include/Peripheral/EXT/Reg/SHAL_EXTI_REG_L432KC.h
View File

@@ -6,7 +6,32 @@
#define SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H
#include "SHAL_CORE.h"
#include "SHAL_EXTI_TYPES.h"
#define EXTI_PENDING_REG(line) ((line) < 32 ? EXTI->PR1 : EXTI->PR2)
static inline SHAL_EXTI_Control_Register getEXTIControlRegister(uint32_t line){
uint8_t maskOffset = line % 4; //Each register has four 4-bit wide fields
uint8_t registerOffset = line / 4; //Composed of four registers with 4 fields each
SHAL_EXTI_Control_Register res = {&SYSCFG->EXTICR[registerOffset], maskOffset};
return res;
}
static inline SHAL_EXTI_Interrupt_Mask_Register getEXTIInterruptMaskRegister(uint32_t line){
volatile uint32_t* reg = line < 32 ? &EXTI->IMR1 : &EXTI->IMR2;
return {reg};;
}
static inline SHAL_EXTI_Rising_Trigger_Selection_Register getEXTIRisingTriggerSelectionRegister(uint32_t line){
volatile uint32_t* reg = line < 32 ? &EXTI->RTSR1 : &EXTI->RTSR2;
return {reg};
}
static inline SHAL_EXTI_Falling_Trigger_Selection_Register getEXTIFallingTriggerSelectionRegister(uint32_t line){
volatile uint32_t* reg = line < 32 ? &EXTI->FTSR1 : &EXTI->FTSR2;
return {reg};
}
#endif //SHMINGO_HAL_SHAL_EXTI_REG_L432KC_H

27
SHAL/Include/Peripheral/EXT/SHAL_EXTI_TYPES.h Normal file
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@@ -0,0 +1,27 @@
//
// Created by Luca on 10/17/2025.
//
#ifndef SHMINGO_HAL_SHAL_EXTI_TYPES_H
#define SHMINGO_HAL_SHAL_EXTI_TYPES_H
#include "SHAL_CORE.h"
struct SHAL_EXTI_Interrupt_Mask_Register {
volatile uint32_t* reg;
};
struct SHAL_EXTI_Rising_Trigger_Selection_Register {
volatile uint32_t* reg;
};
struct SHAL_EXTI_Falling_Trigger_Selection_Register {
volatile uint32_t* reg;
};
struct SHAL_EXTI_Control_Register {
volatile uint32_t* reg;
uint32_t offset;
};
#endif //SHMINGO_HAL_SHAL_EXTI_TYPES_H

238
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h
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@@ -29,66 +29,29 @@ enum class GPIO_Key : uint8_t {
INVALID
};
static volatile GPIO_TypeDef * GPIO_TABLE[3] = { //Lookup table for ADCs
GPIOA,
GPIOB,
GPIOC,
};
constexpr uint8_t getGPIOPinNumber(GPIO_Key key){
return static_cast<uint8_t>(key) % 16;
}
constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {GPIOA,0};
case GPIO_Key::A1: return {GPIOA,1};
case GPIO_Key::A2: return {GPIOA,2};
case GPIO_Key::A3: return {GPIOA,3};
case GPIO_Key::A4: return {GPIOA,4};
case GPIO_Key::A5: return {GPIOA,5};
case GPIO_Key::A6: return {GPIOA,6};
case GPIO_Key::A7: return {GPIOA,7};
case GPIO_Key::A8: return {GPIOA,8};
case GPIO_Key::A9: return {GPIOA,9};
case GPIO_Key::A10: return {GPIOA,10};
case GPIO_Key::A11: return {GPIOA,11};
case GPIO_Key::A12: return {GPIOA,12};
case GPIO_Key::A13: return {GPIOA,13};
case GPIO_Key::A14: return {GPIOA,14};
case GPIO_Key::A15: return {GPIOA,15};
case GPIO_Key::B0: return {GPIOB,0};
case GPIO_Key::B1: return {GPIOB,1};
case GPIO_Key::B2: return {GPIOB,2};
case GPIO_Key::B3: return {GPIOB,3};
case GPIO_Key::B4: return {GPIOB,4};
case GPIO_Key::B5: return {GPIOB,5};
case GPIO_Key::B6: return {GPIOB,6};
case GPIO_Key::B7: return {GPIOB,7};
case GPIO_Key::B8: return {GPIOB,8};
case GPIO_Key::B9: return {GPIOB,9};
case GPIO_Key::B10: return {GPIOB,10};
case GPIO_Key::B11: return {GPIOB,11};
case GPIO_Key::B12: return {GPIOB,12};
case GPIO_Key::B13: return {GPIOB,13};
case GPIO_Key::B14: return {GPIOB,14};
case GPIO_Key::B15: return {GPIOB,15};
case GPIO_Key::C0: return {GPIOC,0};
case GPIO_Key::C1: return {GPIOC,1};
case GPIO_Key::C2: return {GPIOC,2};
case GPIO_Key::C3: return {GPIOC,3};
case GPIO_Key::C4: return {GPIOC,4};
case GPIO_Key::C5: return {GPIOC,5};
case GPIO_Key::C6: return {GPIOC,6};
case GPIO_Key::C7: return {GPIOC,7};
case GPIO_Key::C8: return {GPIOC,8};
case GPIO_Key::C9: return {GPIOC,9};
case GPIO_Key::C10: return {GPIOC,10};
case GPIO_Key::C11: return {GPIOC,11};
case GPIO_Key::C12: return {GPIOC,12};
case GPIO_Key::C13: return {GPIOC,13};
case GPIO_Key::C14: return {GPIOC,14};
case GPIO_Key::C15: return {GPIOC,15};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_GPIO_Peripheral(nullptr,0); //Unreachable
static inline uint32_t getGPIOPortNumber(const GPIO_Key g){
return (static_cast<uint8_t>(g) / 16);
}
__builtin_unreachable();
static inline SHAL_GPIO_RCC_Enable_Register getGPIORCCEnable(const GPIO_Key g){
volatile uint32_t* reg = &RCC->AHBENR; //register
uint32_t mask;
mask = RCC_AHBENR_GPIOAEN << getGPIOPortNumber(g); //Should shift to get each port number
return {reg,mask};
}
constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PA,EXTI0_1_IRQn};
@@ -148,128 +111,55 @@ constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
__builtin_unreachable();
}
constexpr SHAL_Peripheral_Register getGPIORCCEnable(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return {&RCC->AHBENR, RCC_AHBENR_GPIOAEN_Pos};
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return {&RCC->AHBENR, RCC_AHBENR_GPIOBEN_Pos};
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return {&RCC->AHBENR, RCC_AHBENR_GPIOCEN_Pos};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_Peripheral_Register(nullptr,0); //Unreachable
}
__builtin_unreachable();
static inline SHAL_GPIO_Mode_Register getGPIOModeRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->MODER;
uint32_t offset = 2 * (static_cast<uint8_t>(key) % 16);
return {reg,offset};
}
constexpr uint32_t getGPIOPortNumber(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return 0;
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return 1;
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return 2;
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return 0;
}
__builtin_unreachable();
static inline SHAL_GPIO_Pullup_Pulldown_Register getGPIOPUPDRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->PUPDR;
uint32_t offset = 2 * static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Alternate_Function_Register getGPIOAlternateFunctionRegister(const GPIO_Key key){
uint32_t pinNumber = static_cast<uint8_t>(key) % 16; //Number of pin (We need 0-7 to be AFR 1 and 8-15 to be AFR 2)
uint32_t afrIndex = pinNumber < 8 ? 0 : 1;
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->AFR[afrIndex];
uint32_t offset = (pinNumber % 8) * 4; //Increment in groups of four
return {reg,offset};
}
static inline SHAL_GPIO_Output_Speed_Register getGPIOOutputSpeedRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->OSPEEDR;
uint32_t offset = 2 * static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Output_Type_Register getGPIOOutputTypeRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->OTYPER;
uint32_t offset = static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Output_Data_Register getGPIOOutputDataRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->ODR;
uint32_t offset = (static_cast<uint8_t>(key) % 16);
return {reg,offset};
}
static inline SHAL_GPIO_Input_Data_Register getGPIOInputDataRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->IDR;
uint32_t offset = static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
/* TODO reimplement
constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
switch(key){
case GPIO_Key::A0:
@@ -343,6 +233,6 @@ constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
__builtin_unreachable();
}
*/
#endif //SHMINGO_HAL_SHAL_GPIO_REG_F072XB_H

241
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_H753xx.h Normal file
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@@ -0,0 +1,241 @@
//
// Created by Luca on 8/29/2025.
//
#ifndef SHAL_GPIO_REG_H753ZIT6
#define SHAL_GPIO_REG_H753ZIT6
#include <stm32h753xx.h>
#include <cassert>
#include "SHAL_GPIO_TYPES.h"
#define AVAILABLE_PORTS 5
#define PINS_PER_PORT 16
#define NUM_EXTI_LINES 16
#define AVAILABLE_GPIO \
X(A0) X(A1) X(A2) X(A3) X(A4) X(A5) X(A6) X(A7) X(A8) X(A9) X(A10) X(A11) X(A12) X(A13) X(A14) X(A15) \
X(B0) X(B1) X(B2) X(B3) X(B4) X(B5) X(B6) X(B7) X(B8) X(B9) X(B10) X(B11) X(B12) X(B13) X(B14) X(B15) \
X(C0) X(C1) X(C2) X(C3) X(C4) X(C5) X(C6) X(C7) X(C8) X(C9) X(C10) X(C11) X(C12) X(C13) X(C14) X(C15) \
X(D0) X(D1) X(D2) X(D3) X(D4) X(D5) X(D6) X(D7) X(D8) X(D9) X(D10) X(D11) X(D12) X(D13) X(D14) X(D15) \
X(E0) X(E1) X(E2) X(E3) X(E4) X(E5) X(E6) X(E7) X(E8) X(E9) X(E10) X(E11) X(E12) X(E13) X(E14) X(E15) \
//Build enum map of available SHAL_GPIO pins
enum class GPIO_Key : uint8_t {
#define X(key) key,
AVAILABLE_GPIO
#undef X
NUM_GPIO,
INVALID
};
static volatile GPIO_TypeDef * GPIO_TABLE[5] = { //Lookup table for ADCs
GPIOA,
GPIOB,
GPIOC,
GPIOD,
GPIOE,
};
constexpr uint8_t getGPIOPinNumber(GPIO_Key key){
return static_cast<uint8_t>(key) % 16;
}
static uint32_t getGPIOPortNumber(const GPIO_Key g){
return (static_cast<uint8_t>(g) / 16);
}
static SHAL_GPIO_RCC_Enable_Register getGPIORCCEnable(const GPIO_Key g){
volatile uint32_t* reg = &RCC->AHB4ENR; //register
uint32_t mask = RCC_AHB4ENR_GPIOAEN << getGPIOPortNumber(g); //Should shift to get each port number
return {reg,mask};
}
/*
constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PA,EXTI0_IRQn};
case GPIO_Key::A1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PA,EXTI1_IRQn};
case GPIO_Key::A2: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI2_PA,EXTI2_IRQn};
case GPIO_Key::A3: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI3_PA,EXTI3_IRQn};
case GPIO_Key::A4: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI4_PA,EXTI4_15_IRQn};
case GPIO_Key::A5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PA,EXTI4_15_IRQn};
case GPIO_Key::A6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PA,EXTI4_15_IRQn};
case GPIO_Key::A7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PA,EXTI4_15_IRQn};
case GPIO_Key::A8: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI8_PA,EXTI4_15_IRQn};
case GPIO_Key::A9: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI9_PA,EXTI4_15_IRQn};
case GPIO_Key::A10: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI10_PA,EXTI4_15_IRQn};
case GPIO_Key::A11: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI11_PA,EXTI4_15_IRQn};
case GPIO_Key::A12: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI12_PA,EXTI4_15_IRQn};
case GPIO_Key::A13: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI13_PA,EXTI4_15_IRQn};
case GPIO_Key::A14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PA,EXTI4_15_IRQn};
case GPIO_Key::A15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PA,EXTI4_15_IRQn};
case GPIO_Key::B0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PB,EXTI0_1_IRQn};
case GPIO_Key::B1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PB,EXTI0_1_IRQn};
case GPIO_Key::B2: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI2_PB,EXTI2_3_IRQn};
case GPIO_Key::B3: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI3_PB,EXTI2_3_IRQn};
case GPIO_Key::B4: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI4_PB,EXTI4_15_IRQn};
case GPIO_Key::B5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PB,EXTI4_15_IRQn};
case GPIO_Key::B6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PB,EXTI4_15_IRQn};
case GPIO_Key::B7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PB,EXTI4_15_IRQn};
case GPIO_Key::B8: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI8_PB,EXTI4_15_IRQn};
case GPIO_Key::B9: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI9_PB,EXTI4_15_IRQn};
case GPIO_Key::B10: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI10_PB,EXTI4_15_IRQn};
case GPIO_Key::B11: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI11_PB,EXTI4_15_IRQn};
case GPIO_Key::B12: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI12_PB,EXTI4_15_IRQn};
case GPIO_Key::B13: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI13_PB,EXTI4_15_IRQn};
case GPIO_Key::B14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PB,EXTI4_15_IRQn};
case GPIO_Key::B15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PB,EXTI4_15_IRQn};
case GPIO_Key::C0: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI0_PC,EXTI0_1_IRQn};
case GPIO_Key::C1: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI1_PC,EXTI0_1_IRQn};
case GPIO_Key::C2: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI2_PC,EXTI2_3_IRQn};
case GPIO_Key::C3: return {&SYSCFG->EXTICR[0],SYSCFG_EXTICR1_EXTI3_PC,EXTI2_3_IRQn};
case GPIO_Key::C4: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI4_PC,EXTI4_15_IRQn};
case GPIO_Key::C5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PC,EXTI4_15_IRQn};
case GPIO_Key::C6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PC,EXTI4_15_IRQn};
case GPIO_Key::C7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PC,EXTI4_15_IRQn};
case GPIO_Key::C8: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI8_PC,EXTI4_15_IRQn};
case GPIO_Key::C9: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI9_PC,EXTI4_15_IRQn};
case GPIO_Key::C10: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI10_PC,EXTI4_15_IRQn};
case GPIO_Key::C11: return {&SYSCFG->EXTICR[2],SYSCFG_EXTICR3_EXTI11_PC,EXTI4_15_IRQn};
case GPIO_Key::C12: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI12_PC,EXTI4_15_IRQn};
case GPIO_Key::C13: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI13_PC,EXTI4_15_IRQn};
case GPIO_Key::C14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PC,EXTI4_15_IRQn};
case GPIO_Key::C15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PC,EXTI4_15_IRQn};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_GPIO_EXTI_Register(nullptr, 0, EXTI4_15_IRQn); //Unreachable
}
__builtin_unreachable();
}
*/
static inline SHAL_GPIO_Mode_Register getGPIOModeRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->MODER;
uint32_t offset = 2 * (static_cast<uint8_t>(key) % 16);
return {reg,offset};
}
static inline SHAL_GPIO_Pullup_Pulldown_Register getGPIOPUPDRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->PUPDR;
uint32_t offset = 2 * static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Alternate_Function_Register getGPIOAlternateFunctionRegister(const GPIO_Key key){
uint32_t pinNumber = static_cast<uint8_t>(key) % 16; //Number of pin (We need 0-7 to be AFR 1 and 8-15 to be AFR 2)
uint32_t afrIndex = pinNumber < 8 ? 0 : 1;
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->AFR[afrIndex];
uint32_t offset = (pinNumber % 8) * 4; //Increment in groups of four
return {reg,offset};
}
static inline SHAL_GPIO_Output_Speed_Register getGPIOOutputSpeedRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->OSPEEDR;
uint32_t offset = 2 * static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Output_Type_Register getGPIOOutputTypeRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->OTYPER;
uint32_t offset = static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Output_Data_Register getGPIOOutputDataRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->ODR;
uint32_t offset = (static_cast<uint8_t>(key) % 16);
return {reg,offset};
}
static inline SHAL_GPIO_Input_Data_Register getGPIOInputDataRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->IDR;
uint32_t offset = static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
/* TODO reimplement
constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
switch(key){
case GPIO_Key::A0:
case GPIO_Key::B0:
case GPIO_Key::C0:
return {0, SHAL_ADC_Channel::CH0};
case GPIO_Key::A1:
case GPIO_Key::B1:
case GPIO_Key::C1:
return {1, SHAL_ADC_Channel::CH1};
case GPIO_Key::A2:
case GPIO_Key::B2:
case GPIO_Key::C2:
return {2, SHAL_ADC_Channel::CH2};
case GPIO_Key::A3:
case GPIO_Key::B3:
case GPIO_Key::C3:
return {3, SHAL_ADC_Channel::CH3};
case GPIO_Key::A4:
case GPIO_Key::B4:
case GPIO_Key::C4:
return {4, SHAL_ADC_Channel::CH4};
case GPIO_Key::A5:
case GPIO_Key::B5:
case GPIO_Key::C5:
return {5, SHAL_ADC_Channel::CH5};
case GPIO_Key::A6:
case GPIO_Key::B6:
case GPIO_Key::C6:
return {6, SHAL_ADC_Channel::CH6};
case GPIO_Key::A7:
case GPIO_Key::B7:
case GPIO_Key::C7:
return {7, SHAL_ADC_Channel::CH7};
case GPIO_Key::A8:
case GPIO_Key::B8:
case GPIO_Key::C8:
return {8, SHAL_ADC_Channel::CH8};
case GPIO_Key::A9:
case GPIO_Key::B9:
case GPIO_Key::C9:
return {9, SHAL_ADC_Channel::CH9};
case GPIO_Key::A10:
case GPIO_Key::B10:
case GPIO_Key::C10:
return {10, SHAL_ADC_Channel::CH10};
case GPIO_Key::A11:
case GPIO_Key::B11:
case GPIO_Key::C11:
return {11, SHAL_ADC_Channel::CH11};
case GPIO_Key::A12:
case GPIO_Key::B12:
case GPIO_Key::C12:
return {12, SHAL_ADC_Channel::CH12};
case GPIO_Key::A13:
case GPIO_Key::B13:
case GPIO_Key::C13:
return {13, SHAL_ADC_Channel::CH13};
case GPIO_Key::A14:
case GPIO_Key::B14:
case GPIO_Key::C14:
return {14, SHAL_ADC_Channel::CH14};
case GPIO_Key::A15:
case GPIO_Key::B15:
case GPIO_Key::C15:
return {15, SHAL_ADC_Channel::CH15};
case GPIO_Key::NUM_GPIO:
case GPIO_Key::INVALID:
return {0, SHAL_ADC_Channel::CH0};
}
__builtin_unreachable();
}
*/
#endif //SHMINGO_HAL_SHAL_GPIO_REG_H753ZIT6_H

354
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_L432KC.h
View File

@@ -10,83 +10,69 @@
#include "SHAL_GPIO_TYPES.h"
#define AVAILABLE_PORTS 3
#define AVAILABLE_PORTS 2
#define PINS_PER_PORT 16
#define NUM_EXTI_LINES 16
#define AVAILABLE_GPIO \
X(A0) X(A1) X(A2) X(A3) X(A4) X(A5) X(A6) X(A7) X(A8) X(A9) X(A10) X(A11) X(A12) X(A13) X(A14) X(A15) \
X(B0) X(B1) X(B2) X(B3) X(B4) X(B5) X(B6) X(B7) X(B8) X(B9) X(B10) X(B11) X(B12) X(B13) X(B14) X(B15) \
X(C0) X(C1) X(C2) X(C3) X(C4) X(C5) X(C6) X(C7) X(C8) X(C9) X(C10) X(C11) X(C12) X(C13) X(C14) X(C15)
//Build enum map of available SHAL_GPIO pins
enum class GPIO_Key : uint8_t {
#define X(key) key,
AVAILABLE_GPIO
#undef X
A0 = 0,
A1 = 1,
A2 = 2,
A3 = 3,
A4 = 4,
A5 = 5,
A6 = 6,
A7 = 7,
A8 = 8,
A9,
A10,
A11,
A12,
A13,
A14,
A15,
B0,
B1,
B3 = 19, //Offset to compensate for lack of B2
B4,
B5,
B6,
B7,
NUM_GPIO,
INVALID
};
enum class GPIO_Alternate_Function_Mapping {
A0_TIM2CH1 = 0x01,
A1_TIM2CH2 = 0x01,
A2_TIM2CH3 = 0x01,
A3_TIM2CH4 = 0x01,
A5_TIM2CH1 = 0x01,
A6_TIM1BKIN = 0x01,
A7_TIM1CH1N = 0x01,
A8_TIM1CH1 = 0x01,
A9_TIM1CH2 = 0x01,
A10_TIM1CH3 = 0x01,
A11_TIM1CH4 = 0x01,
A12_TIM1ETR = 0x01,
A15_TIM2CH1 = 0x01,
B0_TIM1CH2N = 0x01,
B1_TIM1CH3N = 0x01,
};
static volatile GPIO_TypeDef * GPIO_TABLE[2] = { //Lookup table for ADCs
GPIOA,
GPIOB
};
constexpr SHAL_GPIO_Peripheral getGPIORegister(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0: return {GPIOA,0};
case GPIO_Key::A1: return {GPIOA,1};
case GPIO_Key::A2: return {GPIOA,2};
case GPIO_Key::A3: return {GPIOA,3};
case GPIO_Key::A4: return {GPIOA,4};
case GPIO_Key::A5: return {GPIOA,5};
case GPIO_Key::A6: return {GPIOA,6};
case GPIO_Key::A7: return {GPIOA,7};
case GPIO_Key::A8: return {GPIOA,8};
case GPIO_Key::A9: return {GPIOA,9};
case GPIO_Key::A10: return {GPIOA,10};
case GPIO_Key::A11: return {GPIOA,11};
case GPIO_Key::A12: return {GPIOA,12};
case GPIO_Key::A13: return {GPIOA,13};
case GPIO_Key::A14: return {GPIOA,14};
case GPIO_Key::A15: return {GPIOA,15};
case GPIO_Key::B0: return {GPIOB,0};
case GPIO_Key::B1: return {GPIOB,1};
case GPIO_Key::B2: return {GPIOB,2};
case GPIO_Key::B3: return {GPIOB,3};
case GPIO_Key::B4: return {GPIOB,4};
case GPIO_Key::B5: return {GPIOB,5};
case GPIO_Key::B6: return {GPIOB,6};
case GPIO_Key::B7: return {GPIOB,7};
case GPIO_Key::B8: return {GPIOB,8};
case GPIO_Key::B9: return {GPIOB,9};
case GPIO_Key::B10: return {GPIOB,10};
case GPIO_Key::B11: return {GPIOB,11};
case GPIO_Key::B12: return {GPIOB,12};
case GPIO_Key::B13: return {GPIOB,13};
case GPIO_Key::B14: return {GPIOB,14};
case GPIO_Key::B15: return {GPIOB,15};
case GPIO_Key::C0: return {GPIOC,0};
case GPIO_Key::C1: return {GPIOC,1};
case GPIO_Key::C2: return {GPIOC,2};
case GPIO_Key::C3: return {GPIOC,3};
case GPIO_Key::C4: return {GPIOC,4};
case GPIO_Key::C5: return {GPIOC,5};
case GPIO_Key::C6: return {GPIOC,6};
case GPIO_Key::C7: return {GPIOC,7};
case GPIO_Key::C8: return {GPIOC,8};
case GPIO_Key::C9: return {GPIOC,9};
case GPIO_Key::C10: return {GPIOC,10};
case GPIO_Key::C11: return {GPIOC,11};
case GPIO_Key::C12: return {GPIOC,12};
case GPIO_Key::C13: return {GPIOC,13};
case GPIO_Key::C14: return {GPIOC,14};
case GPIO_Key::C15: return {GPIOC,15};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_GPIO_Peripheral(nullptr,0); //Unreachable
constexpr uint8_t getGPIOPinNumber(GPIO_Key key){
return static_cast<uint8_t>(key) % 16;
}
__builtin_unreachable();
constexpr uint8_t getGPIOPortNUmber(GPIO_Key key){
return static_cast<uint8_t>(key) / 16;
}
constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
@@ -114,8 +100,7 @@ constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
case GPIO_Key::B5: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI5_PB,EXTI9_5_IRQn};
case GPIO_Key::B6: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI6_PB,EXTI9_5_IRQn};
case GPIO_Key::B7: return {&SYSCFG->EXTICR[1],SYSCFG_EXTICR2_EXTI7_PB,EXTI9_5_IRQn};
case GPIO_Key::C14: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI14_PC,EXTI15_10_IRQn};
case GPIO_Key::C15: return {&SYSCFG->EXTICR[3],SYSCFG_EXTICR4_EXTI15_PC,EXTI15_10_IRQn};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
@@ -125,201 +110,118 @@ constexpr SHAL_GPIO_EXTI_Register getGPIOEXTICR(const GPIO_Key g){
__builtin_unreachable();
}
constexpr SHAL_Peripheral_Register getGPIORCCEnable(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN_Pos};
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN_Pos};
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return {&RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN_Pos};
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return SHAL_Peripheral_Register(nullptr,0); //Unreachable
}
__builtin_unreachable();
static inline SHAL_GPIO_RCC_Enable_Register getGPIORCCEnable(const GPIO_Key g){
volatile uint32_t* reg = &RCC->AHB2ENR; //register
uint32_t offset;
offset = RCC_AHB2ENR_GPIOAEN << getGPIOPortNUmber(g); //Should shift to get each port number
return {reg,offset};
}
constexpr uint32_t getGPIOPortNumber(const GPIO_Key g){
switch(g) {
case GPIO_Key::A0:
case GPIO_Key::A1:
case GPIO_Key::A2:
case GPIO_Key::A3:
case GPIO_Key::A4:
case GPIO_Key::A5:
case GPIO_Key::A6:
case GPIO_Key::A7:
case GPIO_Key::A8:
case GPIO_Key::A9:
case GPIO_Key::A10:
case GPIO_Key::A11:
case GPIO_Key::A12:
case GPIO_Key::A13:
case GPIO_Key::A14:
case GPIO_Key::A15:
return 0;
case GPIO_Key::B0:
case GPIO_Key::B1:
case GPIO_Key::B2:
case GPIO_Key::B3:
case GPIO_Key::B4:
case GPIO_Key::B5:
case GPIO_Key::B6:
case GPIO_Key::B7:
case GPIO_Key::B8:
case GPIO_Key::B9:
case GPIO_Key::B10:
case GPIO_Key::B11:
case GPIO_Key::B12:
case GPIO_Key::B13:
case GPIO_Key::B14:
case GPIO_Key::B15:
return 1;
case GPIO_Key::C0:
case GPIO_Key::C1:
case GPIO_Key::C2:
case GPIO_Key::C3:
case GPIO_Key::C4:
case GPIO_Key::C5:
case GPIO_Key::C6:
case GPIO_Key::C7:
case GPIO_Key::C8:
case GPIO_Key::C9:
case GPIO_Key::C10:
case GPIO_Key::C11:
case GPIO_Key::C12:
case GPIO_Key::C13:
case GPIO_Key::C14:
case GPIO_Key::C15:
return 2;
case GPIO_Key::INVALID:
case GPIO_Key::NUM_GPIO:
assert(false);
return 0;
return (static_cast<uint8_t>(g) / 16);
}
__builtin_unreachable();
static inline SHAL_GPIO_Mode_Register getGPIOModeRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->MODER;
uint32_t offset = 2 * (static_cast<uint8_t>(key) % 16);
return {reg,offset};
}
static inline SHAL_GPIO_Pullup_Pulldown_Register getGPIOPUPDRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->PUPDR;
uint32_t offset = 2 * static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Alternate_Function_Register getGPIOAlternateFunctionRegister(const GPIO_Key key){
uint32_t pinNumber = static_cast<uint8_t>(key) % 16; //Number of pin (We need 0-7 to be AFR 1 and 8-15 to be AFR 2)
uint32_t afrIndex = pinNumber < 8 ? 0 : 1;
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->AFR[afrIndex];
uint32_t offset = (pinNumber % 8) * 4; //Increment in groups of four
return {reg,offset};
}
static inline SHAL_GPIO_Output_Speed_Register getGPIOOutputSpeedRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->OSPEEDR;
uint32_t offset = 2 * static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Output_Type_Register getGPIOOutputTypeRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->OTYPER;
uint32_t offset = static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
static inline SHAL_GPIO_Output_Data_Register getGPIOOutputDataRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->ODR;
uint32_t offset = (static_cast<uint8_t>(key) % 16);
return {reg,offset};
}
static inline SHAL_GPIO_Input_Data_Register getGPIOInputDataRegister(const GPIO_Key key){
volatile uint32_t* reg = &GPIO_TABLE[static_cast<uint8_t>(key) / 16]->IDR;
uint32_t offset = static_cast<uint8_t>(key) % 16;
return {reg,offset};
}
constexpr SHAL_GPIO_Port_Info getGPIOPortInfo(GPIO_Key key){
switch(key){
case GPIO_Key::A0:
return {0, SHAL_ADC_Channel::CH5};
case GPIO_Key::B0:
case GPIO_Key::C0:
return {0, SHAL_ADC_Channel::CH0};
return {0, SHAL_ADC_Channel::CH15};
case GPIO_Key::A1:
return {1, SHAL_ADC_Channel::CH6};
case GPIO_Key::B1:
case GPIO_Key::C1:
return {1, SHAL_ADC_Channel::CH1};
return {1, SHAL_ADC_Channel::CH16};
case GPIO_Key::A2:
case GPIO_Key::B2:
case GPIO_Key::C2:
return {2, SHAL_ADC_Channel::CH2};
return {2, SHAL_ADC_Channel::CH7};
case GPIO_Key::A3:
return {3, SHAL_ADC_Channel::CH8};
case GPIO_Key::B3:
case GPIO_Key::C3:
return {3, SHAL_ADC_Channel::CH3};
return {3, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A4:
return {4, SHAL_ADC_Channel::CH9};
case GPIO_Key::B4:
case GPIO_Key::C4:
return {4, SHAL_ADC_Channel::CH4};
return {4, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A5:
return {5, SHAL_ADC_Channel::CH10};
case GPIO_Key::B5:
case GPIO_Key::C5:
return {5, SHAL_ADC_Channel::CH5};
return {5, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A6:
return {6, SHAL_ADC_Channel::CH11};
case GPIO_Key::B6:
case GPIO_Key::C6:
return {6, SHAL_ADC_Channel::CH6};
return {6, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A7:
return {7, SHAL_ADC_Channel::CH12};
case GPIO_Key::B7:
case GPIO_Key::C7:
return {7, SHAL_ADC_Channel::CH7};
return {7, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A8:
case GPIO_Key::B8:
case GPIO_Key::C8:
return {8, SHAL_ADC_Channel::CH8};
return {8, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A9:
case GPIO_Key::B9:
case GPIO_Key::C9:
return {9, SHAL_ADC_Channel::CH9};
return {9, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A10:
case GPIO_Key::B10:
case GPIO_Key::C10:
return {10, SHAL_ADC_Channel::CH10};
return {10, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A11:
case GPIO_Key::B11:
case GPIO_Key::C11:
return {11, SHAL_ADC_Channel::CH11};
return {11, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A12:
case GPIO_Key::B12:
case GPIO_Key::C12:
return {12, SHAL_ADC_Channel::CH12};
return {12, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A13:
case GPIO_Key::B13:
case GPIO_Key::C13:
return {13, SHAL_ADC_Channel::CH13};
return {13, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A14:
case GPIO_Key::B14:
case GPIO_Key::C14:
return {14, SHAL_ADC_Channel::CH14};
return {14, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::A15:
case GPIO_Key::B15:
case GPIO_Key::C15:
return {15, SHAL_ADC_Channel::CH15};
return {15, SHAL_ADC_Channel::NO_ADC_MAPPING};
case GPIO_Key::NUM_GPIO:
case GPIO_Key::INVALID:
return {0, SHAL_ADC_Channel::CH0};
return {0, SHAL_ADC_Channel::NO_ADC_MAPPING};
}
__builtin_unreachable();
}
#endif //SHAL_GPIO_REG_F072XB_H

41
SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
View File

@@ -9,40 +9,41 @@
#include <cassert>
#include "SHAL_EXTI_CALLBACK.h"
#include "SHAL_ADC.h"
//#include "SHAL_EXTI_CALLBACK.h"
//#include "SHAL_ADC.h"
//Abstraction of SHAL_GPIO registers
class SHAL_GPIO{
public:
void toggle() volatile;
void toggle() const volatile;
//TODO replace stupid offset hack from APB
void setHigh();
void setLow();
void setHigh() const;
void setLow() const;
/// Uses the ADC to read an analog voltage value
/// \param sampleTime The amount of clock cycles to use for the ADC
/// \return ADC result
uint16_t analogRead(ADC_SampleTime sampleTime = ADC_SampleTime::C239);
//uint16_t analogRead(SHAL_ADC_SampleTime sampleTime = SHAL_ADC_SampleTime::C8); TODO Reimplement
void setPinMode(PinMode mode) volatile;
uint16_t digitalRead() const;
void setAlternateFunction(GPIO_Alternate_Function AF) volatile;
void setAlternateFunction(GPIO_Alternate_Function AF) const volatile;
//void setAlternateFunction(GPIO_Alternate_Function_Mapping AF) volatile; //TODO reimplement?
void setPinType(PinType type) volatile;
void setOutputType(PinType type) const volatile;
void setOutputSpeed(OutputSpeed speed) volatile;
void setOutputSpeed(OutputSpeed speed) const volatile;
void setInternalResistor(InternalResistorType type) volatile;
void setInternalResistor(InternalResistorType type) const volatile;
//void useAsExternalInterrupt(TriggerMode mode, EXTICallback callback); TODO reimplement
void useAsExternalInterrupt(TriggerMode mode, EXTICallback callback);
SHAL_Result setPinMode(PinMode mode) const volatile;
[[nodiscard]] GPIO_Key getKey() const {return m_GPIO_KEY;};
private:
@@ -65,7 +66,8 @@ private:
#define GET_GPIO(key) GPIOManager::get(key)
#define SET_ANALOGREAD_ADC(x) GPIOManager::setGPIOADC(x)
//#define SET_ANALOGREAD_ADC(x) GPIOManager::setGPIOADC(x) TODO reimplement
//Manages instances of SHAL_GPIO objects
class GPIOManager{
@@ -73,10 +75,13 @@ class GPIOManager{
public:
static SHAL_GPIO& get(GPIO_Key);
static SHAL_GPIO& get(uint8_t portNum, uint8_t pinNum);
static SHAL_ADC getGPIOADC(){ return m_GPIO_ADC;}
static void initGPIO(GPIO_Key key);
static void setGPIOADC(SHAL_ADC adc){m_GPIO_ADC = adc;}
//static SHAL_ADC getGPIOADC(){ return m_GPIO_ADC;} TODO Reimplement
//static void setGPIOADC(SHAL_ADC adc){m_GPIO_ADC = adc;} TODO Reimplement
GPIOManager() = delete;
@@ -84,7 +89,7 @@ private:
inline static SHAL_GPIO m_gpios[AVAILABLE_PORTS][PINS_PER_PORT] = {{}};
inline static SHAL_ADC m_GPIO_ADC = SHAL_ADC(1);
//inline static SHAL_ADC m_GPIO_ADC = SHAL_ADC(1); TODO Reimplement
};

46
SHAL/Include/Peripheral/GPIO/SHAL_GPIO_REG.h
View File

@@ -39,6 +39,50 @@
#include "stm32f030xc.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#elif defined(STM32H743xx)
#include "stm32h743xx.h"
#elif defined(STM32H753xx)
#include "SHAL_GPIO_REG_H753xx.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H745xG)
#include "stm32h745xg.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H747xG)
#include "stm32h747xg.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#elif defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
@@ -95,6 +139,4 @@
#endif
#endif //SHMINGO_HAL_SHAL_GPIO_REG_H

53
SHAL/Include/Peripheral/GPIO/SHAL_GPIO_TYPES.h
View File

@@ -6,8 +6,8 @@
#define SHAL_GPIO_TYPES_H
#include "SHAL_CORE.h"
#include "SHAL_ADC.h"
#include "SHAL_ADC_TYPES.h"
//#include "SHAL_ADC.h"
//#include "SHAL_ADC_TYPES.h"
struct SHAL_GPIO_EXTI_Register{
volatile uint32_t* EXT_ICR; //4 32 bit registers which say which GPIO a line is connected to
@@ -15,21 +15,52 @@ struct SHAL_GPIO_EXTI_Register{
IRQn_Type IRQN; //IRQ number for enabling lines
};
struct SHAL_GPIO_Peripheral {
GPIO_TypeDef * reg;
unsigned long global_offset;
};
struct SHAL_Peripheral_Register {
struct SHAL_GPIO_RCC_Enable_Register{
volatile uint32_t* reg;
unsigned long offset;
uint32_t mask;
};
struct SHAL_GPIO_Mode_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_GPIO_Pullup_Pulldown_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_GPIO_Alternate_Function_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_GPIO_Output_Speed_Register{
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_GPIO_Output_Type_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_GPIO_Output_Data_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_GPIO_Input_Data_Register {
volatile uint32_t* reg;
uint32_t offset;
};
/* TODO reimplement and uncomment ADC references (Here and on GPIO.h)
struct SHAL_GPIO_Port_Info{
uint8_t number;
SHAL_ADC_Channel ADCChannel;
};
*/
enum class PinMode : uint8_t{
INPUT_MODE = 0x00,
OUTPUT_MODE = 0x01,
@@ -74,4 +105,4 @@ enum class TriggerMode : uint8_t{
};
#endif //SHMINGO_HAL_SHAL_GPIO_TYPES_H
#endif //SHAL_GPIO_TYPES_H

5
SHAL/Include/Peripheral/I2C/Reg/SHAL_I2C_REG_L432KC.h
View File

@@ -8,6 +8,8 @@
#include "SHAL_CORE.h"
#include "SHAL_I2C_TYPES.h"
#define NUM_I2C_BUSES 3
enum class I2C_Pair : uint8_t{
//I2C_1
SCL1A9_SDA1A10, //AF4
@@ -62,9 +64,6 @@ constexpr SHAL_I2C_Reset_Reg getI2CResetReg(const I2C_Pair pair){
__builtin_unreachable();
}
constexpr SHAL_I2C_Reset_Reg getI2CResetRe() {
return {&RCC->APB1RSTR1,RCC_APB1RSTR1_I2C1RST};
}
//Gets all the bits in the I2C timer register, these values should rarely be manually set, but I wanted to support it anyway
constexpr SHAL_I2C_Timing_Reg getI2CTimerReg(const I2C_Pair pair){
switch(pair){

235
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_F072xB.h
View File

@@ -6,8 +6,8 @@
******************************************************************************
*/
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#ifndef SHAL_TIM_REG_F072XB_H
#define SHAL_TIM_REG_F072XB_H
#include <cassert>
#include <stm32f072xb.h>
@@ -16,9 +16,9 @@
#include "SHAL_TIM_TYPES.h"
enum class Timer_Key : uint8_t { //For STM32F072
S_TIM1,
S_TIM2,
S_TIM3,
S_TIM1 = 0,
S_TIM2 = 1,
S_TIM3 = 2,
S_TIM6,
S_TIM7,
S_TIM14,
@@ -39,20 +39,40 @@ enum class Timer_Key : uint8_t { //For STM32F072
#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
#define SHAL_TIM17 TimerManager::get(Timer_Key::S_TIM17)
static SHAL_TIM_Info TIM_INFO_TABLE[9] = {
{TIM1,TIM1_BRK_UP_TRG_COM_IRQn,4},
{TIM2,TIM2_IRQn,4},
{TIM3,TIM3_IRQn,4},
{TIM6,TIM6_DAC_IRQn,0},
{TIM7,TIM7_IRQn,0},
{TIM14,TIM14_IRQn,1},
{TIM15,TIM15_IRQn,2},
{TIM16,TIM16_IRQn,1},
{TIM17,TIM17_IRQn,1},
};
//Get actual register value based on enum
static volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
return TIM_INFO_TABLE[static_cast<uint8_t>(t)].timer;
}
static IRQn_Type getIRQn(Timer_Key t) {
return TIM_INFO_TABLE[static_cast<uint8_t>(t)].IRQn;
}
//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
constexpr TIM_RCC_Enable getTimerRCC(Timer_Key t) {
static SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN_Pos};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR, RCC_APB1ENR_TIM2EN_Pos};
case Timer_Key::S_TIM3: return {&RCC->APB1ENR, RCC_APB1ENR_TIM3EN_Pos};
case Timer_Key::S_TIM6: return {&RCC->APB1ENR, RCC_APB1ENR_TIM6EN_Pos};
case Timer_Key::S_TIM7: return {&RCC->APB1ENR, RCC_APB1ENR_TIM7EN_Pos};
case Timer_Key::S_TIM14: return {&RCC->APB1ENR, RCC_APB1ENR_TIM14EN_Pos};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN_Pos};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN_Pos};
case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN_Pos};
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR, RCC_APB1ENR_TIM2EN};
case Timer_Key::S_TIM3: return {&RCC->APB1ENR, RCC_APB1ENR_TIM3EN};
case Timer_Key::S_TIM6: return {&RCC->APB1ENR, RCC_APB1ENR_TIM6EN};
case Timer_Key::S_TIM7: return {&RCC->APB1ENR, RCC_APB1ENR_TIM7EN};
case Timer_Key::S_TIM14: return {&RCC->APB1ENR, RCC_APB1ENR_TIM14EN};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
@@ -62,43 +82,162 @@ constexpr TIM_RCC_Enable getTimerRCC(Timer_Key t) {
__builtin_unreachable();
}
//Get actual register value based on enum
constexpr volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return TIM1;
case Timer_Key::S_TIM2: return TIM2;
case Timer_Key::S_TIM3: return TIM3;
case Timer_Key::S_TIM6: return TIM6;
case Timer_Key::S_TIM7: return TIM7;
case Timer_Key::S_TIM14: return TIM14;
case Timer_Key::S_TIM15: return TIM15;
case Timer_Key::S_TIM16: return TIM16;
case Timer_Key::S_TIM17: return TIM17;
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
return nullptr; //Unreachable
}
__builtin_unreachable();
static SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->SR;
return res;
}
constexpr IRQn_Type getIRQn(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return TIM1_BRK_UP_TRG_COM_IRQn;
case Timer_Key::S_TIM2: return TIM2_IRQn;
case Timer_Key::S_TIM3: return TIM3_IRQn;
case Timer_Key::S_TIM6: return TIM6_DAC_IRQn;
case Timer_Key::S_TIM7: return TIM7_IRQn;
case Timer_Key::S_TIM14: return TIM14_IRQn;
case Timer_Key::S_TIM15: return TIM15_IRQn;
case Timer_Key::S_TIM16: return TIM16_IRQn;
case Timer_Key::S_TIM17: return TIM17_IRQn;
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
return TIM1_BRK_UP_TRG_COM_IRQn; //Unreachable
static SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk,
TIM_CR1_UDIS,
TIM_CR1_OPM,
TIM_CR1_CMS_Pos,
TIM_CR1_ARPE};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->CR1;
return res;
}
static SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->DIER;
return res;
}
static SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->EGR;
return res;
}
static SHAL_TIM_Break_Dead_Time_Register getTimerBreakDeadTimeRegister(Timer_Key key) {
SHAL_TIM_Break_Dead_Time_Register res = {nullptr,
TIM_BDTR_DTG_Pos,
TIM_BDTR_LOCK_Pos,
TIM_BDTR_OSSI,
TIM_BDTR_OSSR,
TIM_BDTR_BKE,
TIM_BDTR_BKP,
TIM_BDTR_AOE,
TIM_BDTR_MOE};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->BDTR;
return res;
}
static SHAL_TIM_Prescaler_Register getTimerPrescalerRegister(Timer_Key key){
SHAL_TIM_Prescaler_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->PSC;
return res;
}
static SHAL_TIM_Auto_Reload_Register getTimerAutoReloadRegister(Timer_Key key){
SHAL_TIM_Auto_Reload_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->ARR;
return res;
}
static SHAL_TIM_Capture_Compare_Register getTimerCaptureCompareRegister(Timer_Key key, SHAL_Timer_Channel channel){
const auto channel_num = static_cast<uint8_t>(channel);
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
assert(channel_num <= TIM_INFO_TABLE[static_cast<uint8_t>(key)].numChannels);
switch(channel){
case SHAL_Timer_Channel::CH1: return {&tim->CCR1,0};
case SHAL_Timer_Channel::CH2: return {&tim->CCR2,0};
case SHAL_Timer_Channel::CH3: return {&tim->CCR3,0};
case SHAL_Timer_Channel::CH4: return {&tim->CCR4,0};
}
__builtin_unreachable();
}
static SHAL_TIM_Capture_Compare_Enable_Register getTimerCaptureCompareEnableRegister(Timer_Key key, SHAL_Timer_Channel channel){
constexpr uint8_t channel_stride = 3;
const auto channel_num = static_cast<uint8_t>(channel);
const auto output_enable = TIM_CCER_CC1E << (channel_stride * (channel_num - 1));
const auto output_polarity = TIM_CCER_CC1P << (channel_stride * channel_num);
const auto output_complimentary_enable = TIM_CCER_CC1NE << (channel_stride * channel_num);
const auto output_complimentary_polarity = TIM_CCER_CC1NP << (channel_stride * channel_num);
SHAL_TIM_Capture_Compare_Enable_Register res = {nullptr,
output_enable,
output_polarity,
output_complimentary_enable,
output_complimentary_polarity,
};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->CCER;
return res;
}
static SHAL_TIM_Output_Capture_Compare_Mode_Register getTimerOutputCaptureCompareModeRegister(Timer_Key key, SHAL_Timer_Channel channel) {
SHAL_TIM_Output_Capture_Compare_Mode_Register res = {
nullptr,
TIM_CCMR1_CC1S_Pos, //Channel 1 Capture/Compare selection
TIM_CCMR1_OC1FE, //Channel 1 Fast enable
TIM_CCMR1_OC1PE, //Channel 1 Preload enable
TIM_CCMR1_OC1M_Pos, //Channel 1 Mode (OC1M)
TIM_CCMR1_OC1CE, //Channel 1 Clear enable
TIM_CCMR1_CC2S_Pos, //Channel 2 Capture/Compare selection
TIM_CCMR1_OC2FE, //Channel 2 Fast enable
TIM_CCMR1_OC2PE, //Channel 2 Preload enable
TIM_CCMR1_OC2M_Pos, //Channel 2 Mode (OC2M)
TIM_CCMR1_OC2CE //Channel 2 Clear enable
};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
const uint8_t num_tim_channels = TIM_INFO_TABLE[static_cast<uint8_t>(key)].numChannels;
volatile uint32_t* reg = nullptr;
const auto channelNum = static_cast<uint32_t>(channel);
assert(num_tim_channels >= channelNum); //Assert that we don't access undefined memory trying to initialize a non-existent channel
if(channelNum >= 3){
reg = &tim->CCMR2;
}
else{
reg = &tim->CCMR1;
}
res.reg = reg;
return res;
}

265
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_H753xx.h Normal file
View File

@@ -0,0 +1,265 @@
/**
******************************************************************************
* @file SHAL_TIM_REG.h
* @author Luca Lizaranzu
* @brief Defines universal macros and objects used across all STM32 families
******************************************************************************
*/
#ifndef SHAL_TIM_REG_H753ZIT6
#define SHAL_TIM_REG_H753ZIT6
#include <cassert>
#include <stm32h753xx.h>
#include "SHAL_CORE.h"
#include "SHAL_TIM_TYPES.h"
enum class Timer_Key : uint8_t { //For STM32F072
S_TIM1 = 0,
S_TIM2 = 1,
S_TIM3 = 2,
S_TIM4,
S_TIM5,
S_TIM6,
S_TIM7,
S_TIM8,
S_TIM12,
S_TIM13,
S_TIM14,
S_TIM15,
S_TIM16,
S_TIM17,
NUM_TIMERS,
S_TIM_INVALID
};
#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
#define SHAL_TIM3 TimerManager::get(Timer_Key::S_TIM3)
#define SHAL_TIM4 TimerManager::get(Timer_Key::S_TIM4)
#define SHAL_TIM5 TimerManager::get(Timer_Key::S_TIM5)
#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
#define SHAL_TIM8 TimerManager::get(Timer_Key::S_TIM8)
#define SHAL_TIM12 TimerManager::get(Timer_Key::S_TIM12)
#define SHAL_TIM13 TimerManager::get(Timer_Key::S_TIM13)
#define SHAL_TIM14 TimerManager::get(Timer_Key::S_TIM14)
#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
#define SHAL_TIM17 TimerManager::get(Timer_Key::S_TIM17)
static SHAL_TIM_Info TIM_INFO_TABLE[14] = {
{TIM1,TIM1_TRG_COM_IRQn,4},
{TIM2,TIM2_IRQn,4},
{TIM3,TIM3_IRQn,4},
{TIM3,TIM4_IRQn,4},
{TIM3,TIM5_IRQn,4},
{TIM6,TIM6_DAC_IRQn,0},
{TIM7,TIM7_IRQn,0},
{TIM8,TIM8_TRG_COM_TIM14_IRQn,6},
{TIM12,TIM8_BRK_TIM12_IRQn,2},
{TIM13,TIM8_UP_TIM13_IRQn,1},
{TIM14,TIM8_TRG_COM_TIM14_IRQn,1},
{TIM15,TIM15_IRQn,2},
{TIM16,TIM16_IRQn,1},
{TIM17,TIM17_IRQn,1},
};
//Get actual register value based on enum
static volatile TIM_TypeDef* getTimerRegister(Timer_Key t) {
return TIM_INFO_TABLE[static_cast<uint8_t>(t)].timer;
}
static IRQn_Type getIRQn(Timer_Key t) {
return TIM_INFO_TABLE[static_cast<uint8_t>(t)].IRQn;
}
//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
static SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
case Timer_Key::S_TIM2: return {&RCC->APB1LENR, RCC_APB1LENR_TIM2EN};
case Timer_Key::S_TIM3: return {&RCC->APB1LENR, RCC_APB1LENR_TIM3EN};
case Timer_Key::S_TIM4: return {&RCC->APB1LENR, RCC_APB1LENR_TIM4EN};
case Timer_Key::S_TIM5: return {&RCC->APB1LENR, RCC_APB1LENR_TIM5EN};
case Timer_Key::S_TIM6: return {&RCC->APB1LENR, RCC_APB1LENR_TIM6EN};
case Timer_Key::S_TIM7: return {&RCC->APB1LENR, RCC_APB1LENR_TIM7EN};
case Timer_Key::S_TIM8: return {&RCC->APB1LENR, RCC_APB2ENR_TIM8EN};
case Timer_Key::S_TIM14: return {&RCC->APB1LENR, RCC_APB1LENR_TIM12EN};
case Timer_Key::S_TIM12: return {&RCC->APB1LENR, RCC_APB1LENR_TIM13EN};
case Timer_Key::S_TIM13: return {&RCC->APB1LENR, RCC_APB1LENR_TIM14EN};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
return {nullptr, 0};; //Unreachable
}
__builtin_unreachable();
}
static SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->SR;
return res;
}
static SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk,
TIM_CR1_UDIS,
TIM_CR1_OPM,
TIM_CR1_CMS_Pos,
TIM_CR1_ARPE};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->CR1;
return res;
}
static SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->DIER;
return res;
}
static SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->EGR;
return res;
}
static SHAL_TIM_Break_Dead_Time_Register getTimerBreakDeadTimeRegister(Timer_Key key) {
SHAL_TIM_Break_Dead_Time_Register res = {nullptr,
TIM_BDTR_DTG_Pos,
TIM_BDTR_LOCK_Pos,
TIM_BDTR_OSSI,
TIM_BDTR_OSSR,
TIM_BDTR_BKE,
TIM_BDTR_BKP,
TIM_BDTR_AOE,
TIM_BDTR_MOE};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->BDTR;
return res;
}
static SHAL_TIM_Prescaler_Register getTimerPrescalerRegister(Timer_Key key){
SHAL_TIM_Prescaler_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->PSC;
return res;
}
static SHAL_TIM_Auto_Reload_Register getTimerAutoReloadRegister(Timer_Key key){
SHAL_TIM_Auto_Reload_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->ARR;
return res;
}
static SHAL_TIM_Capture_Compare_Register getTimerCaptureCompareRegister(Timer_Key key, SHAL_Timer_Channel channel){
const auto channel_num = static_cast<uint8_t>(channel);
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
assert(channel_num <= TIM_INFO_TABLE[static_cast<uint8_t>(key)].numChannels);
switch(channel){
case SHAL_Timer_Channel::CH1: return {&tim->CCR1,0};
case SHAL_Timer_Channel::CH2: return {&tim->CCR2,0};
case SHAL_Timer_Channel::CH3: return {&tim->CCR3,0};
case SHAL_Timer_Channel::CH4: return {&tim->CCR4,0};
}
__builtin_unreachable();
}
static SHAL_TIM_Capture_Compare_Enable_Register getTimerCaptureCompareEnableRegister(Timer_Key key, SHAL_Timer_Channel channel){
constexpr uint8_t channel_stride = 3;
const auto channel_num = static_cast<uint8_t>(channel);
const auto output_enable = TIM_CCER_CC1E << (channel_stride * (channel_num - 1));
const auto output_polarity = TIM_CCER_CC1P << (channel_stride * channel_num);
const auto output_complimentary_enable = TIM_CCER_CC1NE << (channel_stride * channel_num);
const auto output_complimentary_polarity = TIM_CCER_CC1NP << (channel_stride * channel_num);
SHAL_TIM_Capture_Compare_Enable_Register res = {nullptr,
output_enable,
output_polarity,
output_complimentary_enable,
output_complimentary_polarity,
};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
res.reg = &tim->CCER;
return res;
}
static SHAL_TIM_Output_Capture_Compare_Mode_Register getTimerOutputCaptureCompareModeRegister(Timer_Key key, SHAL_Timer_Channel channel) {
SHAL_TIM_Output_Capture_Compare_Mode_Register res = {
nullptr,
TIM_CCMR1_CC1S_Pos, //Channel 1 Capture/Compare selection
TIM_CCMR1_OC1FE, //Channel 1 Fast enable
TIM_CCMR1_OC1PE, //Channel 1 Preload enable
TIM_CCMR1_OC1M_Pos, //Channel 1 Mode (OC1M)
TIM_CCMR1_OC1CE, //Channel 1 Clear enable
TIM_CCMR1_CC2S_Pos, //Channel 2 Capture/Compare selection
TIM_CCMR1_OC2FE, //Channel 2 Fast enable
TIM_CCMR1_OC2PE, //Channel 2 Preload enable
TIM_CCMR1_OC2M_Pos, //Channel 2 Mode (OC2M)
TIM_CCMR1_OC2CE //Channel 2 Clear enable
};
volatile TIM_TypeDef* tim = TIM_INFO_TABLE[static_cast<uint8_t>(key)].timer;
const uint8_t num_tim_channels = TIM_INFO_TABLE[static_cast<uint8_t>(key)].numChannels;
volatile uint32_t* reg = nullptr;
const auto channelNum = static_cast<uint32_t>(channel);
assert(num_tim_channels >= channelNum); //Assert that we don't access undefined memory trying to initialize a non-existent channel
if(channelNum >= 3){
reg = &tim->CCMR2;
}
else{
reg = &tim->CCMR1;
}
res.reg = reg;
return res;
}
#endif

205
SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_L432KC.h Normal file
View File

@@ -0,0 +1,205 @@
/**
******************************************************************************
* @file SHAL_TIM_REG.h
* @author Luca Lizaranzu
* @brief Defines universal macros and objects used across all STM32 families
******************************************************************************
*/
#ifndef SHAL_TIM_REG_L432KC_H
#define SHAL_TIM_REG_L432KC_H
#include <cassert>
#include <stm32l432xx.h>
#include "SHAL_CORE.h"
#include "SHAL_TIM_TYPES.h"
enum class Timer_Key : uint8_t { //For STM32L432
S_TIM1,
S_TIM2,
S_TIM6,
S_TIM7,
S_TIM15,
S_TIM16,
NUM_TIMERS,
S_TIM_INVALID
};
//Lookup table for timer typedefs
static volatile TIM_TypeDef* TIM_TABLE[6] = {
TIM1,
TIM2,
TIM6,
TIM7,
TIM15,
TIM16,
};
static IRQn_Type IRQN_TABLE[6] = {
TIM1_TRG_COM_IRQn,
TIM2_IRQn,
TIM6_DAC_IRQn,
TIM7_IRQn,
TIM1_BRK_TIM15_IRQn,
TIM1_UP_TIM16_IRQn
};
#define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
#define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
#define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
#define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
#define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
#define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
static inline SHAL_TIM_Status_Register getTimerStatusRegister(Timer_Key key){
SHAL_TIM_Status_Register res = {nullptr, TIM_SR_UIF};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->SR;
return res;
}
static inline SHAL_TIM_Control_Register_1 getTimerControlRegister1(Timer_Key key){
SHAL_TIM_Control_Register_1 res = {nullptr, TIM_CR1_CEN_Msk,
TIM_CR1_UDIS,
TIM_CR1_OPM,
TIM_CR1_CMS_Pos,
TIM_CR1_ARPE};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->CR1;
return res;
}
static inline SHAL_TIM_DMA_Interrupt_Enable_Register getTimerDMAInterruptEnableRegister(Timer_Key key){
SHAL_TIM_DMA_Interrupt_Enable_Register res = {nullptr, TIM_DIER_UIE};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->DIER;
return res;
}
static inline SHAL_TIM_Event_Generation_Register getTimerEventGenerationRegister(Timer_Key key){
SHAL_TIM_Event_Generation_Register res = {nullptr, TIM_EGR_UG};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->EGR;
return res;
}
static inline SHAL_TIM_Prescaler_Register getTimerPrescalerRegister(Timer_Key key){
SHAL_TIM_Prescaler_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->PSC;
return res;
}
static inline SHAL_TIM_Auto_Reload_Register getTimerAutoReloadRegister(Timer_Key key){
SHAL_TIM_Auto_Reload_Register res = {nullptr, 1UL << 15};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->ARR;
return res;
}
//Get TIMER_KEY peripheral struct including bus register, enable mask, TIMER_KEY mask
static inline SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
switch(t) {
case Timer_Key::S_TIM1: return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
case Timer_Key::S_TIM2: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN};
case Timer_Key::S_TIM6: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN};
case Timer_Key::S_TIM7: return {&RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN};
case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
case Timer_Key::NUM_TIMERS:
case Timer_Key::S_TIM_INVALID:
assert(false);
}
__builtin_unreachable();
}
static inline SHAL_TIM_Capture_Compare_Mode_Registers_Input getTimerCaptureCompareModeRegisters(Timer_Key key){
SHAL_TIM_Capture_Compare_Mode_Registers_Input res = {{nullptr,
nullptr},
TIM_CCMR1_CC1S_Pos,
TIM_CCMR1_IC1PSC_Pos,
TIM_CCMR1_IC1F_Pos,
TIM_CCMR1_CC2S_Pos,
TIM_CCMR1_IC2PSC_Pos,
TIM_CCMR1_IC2F_Pos
};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.regs[0] = &tim->CCMR1;
res.regs[1] = &tim->CCMR2;
return res;
}
static inline SHAL_TIM_Capture_Compare_Mode_Registers_Output
getTimerCaptureCompareModeRegistersOutput(Timer_Key key) {
SHAL_TIM_Capture_Compare_Mode_Registers_Output res = {
{nullptr, nullptr},
TIM_CCMR1_CC1S_Pos, //Channel 1 Capture/Compare selection
TIM_CCMR1_OC1FE, //Channel 1 Fast enable
TIM_CCMR1_OC1PE, //Channel 1 Preload enable
TIM_CCMR1_OC1M_Pos, //Channel 1 Mode (OC1M)
TIM_CCMR1_OC1CE, //Channel 1 Clear enable
TIM_CCMR1_CC2S_Pos, //Channel 2 Capture/Compare selection
TIM_CCMR1_OC2FE, //Channel 2 Fast enable
TIM_CCMR1_OC2PE, //Channel 2 Preload enable
TIM_CCMR1_OC2M_Pos, //Channel 2 Mode (OC2M)
TIM_CCMR1_OC2CE //Channel 2 Clear enable
};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.regs[0] = &tim->CCMR1;
res.regs[1] = &tim->CCMR2;
return res;
}
static inline SHAL_TIM_Break_Dead_Time_Register getTimerBreakDeadTimeRegister(Timer_Key key){
SHAL_TIM_Break_Dead_Time_Register res = {nullptr, TIM_BDTR_MOE};
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
res.reg = &tim->BDTR;
return res;
}
static inline SHAL_TIM_Capture_Compare_Enable_Register getTimerCaptureCompareEnableRegister(Timer_Key key){
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
return {&tim->CCER};
}
static inline SHAL_TIM_Capture_Compare_Register getTimerCaptureCompareRegister(Timer_Key key){
volatile TIM_TypeDef* tim = TIM_TABLE[static_cast<uint8_t>(key)];
return {&tim->CCR2};
}
//Get timer IRQN from lookup table
static inline IRQn_Type getTimerIRQn(Timer_Key t) {
return IRQN_TABLE[static_cast<uint8_t>(t)];
}
#endif

36
SHAL/Include/Peripheral/Timer/SHAL_TIM.h
View File

@@ -9,7 +9,7 @@
#ifndef SHAL_TIM_H
#define SHAL_TIM_H
#include "SHAL_TIM_REG_F072xB.h"
#include "SHAL_TIM_REG.h"
#include "SHAL_TIM_CALLBACK.h"
#include <array>
@@ -18,29 +18,48 @@ class Timer {
friend class TimerManager;
public:
///
/// Initializes a timer
/// \param prescaler The amount of times the base clock has to cycle before the timer adds one to the count
/// \param autoReload The number of timer counts before the count is reset and IRQ is called
void init(uint32_t prescaler, uint32_t autoReload);
void init() const; //Empty init (enable RCC)
/// Simple function to set a timer in basic PWM mode
/// @param channel Channel to output on
/// @param prescaler Divider from sysclock
/// @param autoReload Counter value to reset at
/// @param captureCompareThreshold PWM trigger value (duty cycle = this / autoReload)
void configurePWM(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold);
void configureOneshot(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold);
//Starts the counter
void start();
//Stops the counter
void stop();
void stop() const;
//Set prescaler value
void setPrescaler(uint16_t presc);
void setPrescaler(uint32_t presc) const;
//Set auto reload register
void setARR(uint16_t arr);
void setARR(uint32_t arr) const;
//Enable interrupts
void enableInterrupt();
//Capture Compare Functions
void setCaptureCompareValue(SHAL_Timer_Channel channel, uint32_t value) const;
void enableChannel(SHAL_Timer_Channel channel, SHAL_Timer_Channel_Main_Output_Mode mainOutputMode, SHAL_Timer_Channel_Complimentary_Output_Mode complimentaryOutputMode);
void setOutputCompareMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode) const;
//Set TIMER_KEY IRQ callback function
void setCallbackFunc(TimerCallback callback){
registerTimerCallback(TIMER_KEY, callback);
void setCallbackFunc(TimerCallback callback) const {
registerTimerCallback(m_key, callback);
}
private:
@@ -48,7 +67,8 @@ private:
explicit Timer(Timer_Key t);
Timer();
Timer_Key TIMER_KEY;
Timer_Key m_key;
};

7
SHAL/Include/Peripheral/Timer/SHAL_TIM_CALLBACK.h
View File

@@ -13,11 +13,12 @@
#include "SHAL_CORE.h"
#include "SHAL_TIM_REG.h"
#define DEFINE_TIMER_IRQ(key, irq_handler) \
extern "C" void irq_handler(void) { \
auto tim_reg = getTimerRegister(key); \
if (tim_reg->SR & TIM_SR_UIF) { \
tim_reg->SR &= ~TIM_SR_UIF; /* clear flag */ \
auto tim_status_reg = getTimerStatusRegister(key); \
if (*tim_status_reg.reg & tim_status_reg.update_interrupt_flag_mask) { \
SHAL_clear_bitmask(tim_status_reg.reg,tim_status_reg.update_interrupt_flag_mask); /* clear flag */ \
auto cb = timer_callbacks[static_cast<int>(key)]; \
if (cb) cb(); \
}; \

56
SHAL/Include/Peripheral/Timer/SHAL_TIM_REG.h
View File

@@ -2,8 +2,8 @@
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_REG_H
#define SHMINGO_HAL_SHAL_TIM_REG_H
#ifndef SHAL_TIM_REG_H
#define SHAL_TIM_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
@@ -46,7 +46,7 @@
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#include "SHAL_TIM_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
@@ -88,8 +88,52 @@
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#elif defined(STM32H743xx)
#include "stm32h743xx.h"
#elif defined(STM32H753xx)
#include "SHAL_TIM_REG_H753xx.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H745xG)
#include "stm32h745xg.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H747xG)
#include "stm32h747xg.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_TIM_REG_H
#error "Please select first the target device used in your application"
#endif
#endif //SHAL_TIM_REG_H

137
SHAL/Include/Peripheral/Timer/SHAL_TIM_TYPES.h
View File

@@ -2,14 +2,141 @@
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_TIM_TYPES_H
#define SHMINGO_HAL_SHAL_TIM_TYPES_H
#ifndef SHAL_TIM_TYPES_H
#define SHAL_TIM_TYPES_H
#include "SHAL_CORE.h"
struct TIM_RCC_Enable{
volatile uint32_t* busEnableReg;
struct SHAL_TIM_Info{
volatile TIM_TypeDef* timer;
IRQn_Type IRQn;
uint8_t numChannels;
};
struct SHAL_TIM_RCC_Register{
volatile uint32_t* reg;
uint32_t enable_mask;
};
struct SHAL_TIM_Control_Register_1 {
volatile uint32_t* reg;
uint32_t counter_enable_mask;
uint32_t update_disable_mask;
uint32_t one_pulse_mode_mask;
uint32_t center_align_mode_offset;
uint32_t auto_reload_preload_enable_mask;
};
struct SHAL_TIM_DMA_Interrupt_Enable_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_enable_mask;
};
struct SHAL_TIM_Status_Register {
volatile uint32_t* reg;
uint32_t update_interrupt_flag_mask;
};
struct SHAL_TIM_Event_Generation_Register {
volatile uint32_t* reg;
uint32_t update_generation_mask;
};
struct SHAL_TIM_Prescaler_Register {
volatile uint32_t* reg;
uint32_t offset;
};
#endif //SHMINGO_HAL_SHAL_TIM_TYPES_H
struct SHAL_TIM_Auto_Reload_Register {
volatile uint32_t* reg;
uint32_t offset;
};
struct SHAL_TIM_Capture_Compare_Mode_Registers_Input {
volatile uint32_t* regs;
uint32_t input_capture_1_filter_offset;
uint32_t input_capture_1_prescaler_offset;
uint32_t capture_compare_1_selection_offset;
uint32_t input_capture_2_filter_offset;
uint32_t input_capture_2_prescaler_offset;
uint32_t capture_compare_2_selection_offset;
};
struct SHAL_TIM_Output_Capture_Compare_Mode_Register {
volatile uint32_t* reg;
uint32_t capture_compare_1_selection_offset;
uint32_t output_compare_1_fast_enable_mask;
uint32_t output_compare_1_preload_enable_mask;
uint32_t output_compare_1_mode_offset;
uint32_t output_compare_1_clear_enable_mask;
uint32_t capture_compare_2_selection_offset;
uint32_t output_compare_2_fast_enable_mask;
uint32_t output_compare_2_preload_enable_mask;
uint32_t output_compare_2_mode_offset;
uint32_t output_compare_2_clear_enable_mask;
};
struct SHAL_TIM_Break_Dead_Time_Register {
volatile uint32_t* reg;
uint32_t dead_time_offset; // [7:0] DTG - Dead-time generator setup
uint32_t lock_configuration_offset; // [9:8] LOCK - Lock configuration
uint32_t off_state_selection_idle_mask; // [10] OSSI - Off-state selection for idle mode
uint32_t off_state_selection_run_mask; // [11] OSSR - Off-state selection for run mode
uint32_t break_enable_mask; // [12] BKE - Break enable
uint32_t break_polarity_mask; // [13] BKP - Break polarity
uint32_t automatic_output_enable_mask; // [14] AOE - Automatic output enable
uint32_t main_output_enable_mask; // [15] MOE - Main output enable
};
struct SHAL_TIM_Capture_Compare_Enable_Register {
volatile uint32_t* reg;
uint32_t cc_output_enable_offset;
uint32_t cc_output_polarity_offset;
uint32_t cc_complimentary_output_enable_offset;
uint32_t cc_complimentary_output_polarity_offset;
};
struct SHAL_TIM_Capture_Compare_Register {
volatile uint32_t* reg;
uint32_t offset;
};
enum class SHAL_TIM_Output_Compare_Mode : uint8_t {
Frozen = 0b000, //Output compare frozen
ActiveOnMatch = 0b001, //Set output to active level on match
InactiveOnMatch = 0b010, //Set output to inactive level on match
Toggle = 0b011, //Toggle output on match
ForceInactive = 0b100, //Force output to inactive
ForceActive = 0b101, //Force output to active
PWMMode1 = 0b110, //PWM mode 1 (active until compare match)
PWMMode2 = 0b111, //PWM mode 2 (inactive until compare match)
};
enum class SHAL_TIM_Output_Compare_Preload : uint8_t {
Disabled = 0b0, //CCRx register is updated immediately
Enabled = 0b1, //CCRx register is buffered; updated on update event (UEV)
};
enum class SHAL_Timer_Channel : uint8_t { //TODO change if other timers have fewer than 6 channels
CH1 = 1,
CH2 = 2,
CH3 = 3,
CH4 = 4,
};
enum class SHAL_Timer_Channel_Main_Output_Mode : uint8_t {
Disabled = 0b00,
Polarity_Normal = 0b01,
Polarity_Reversed = 0b11,
};
enum class SHAL_Timer_Channel_Complimentary_Output_Mode : uint8_t {
Disabled = 0b00,
Polarity_Normal = 0b01,
Polarity_Reversed = 0b11,
};
#endif //SHAL_TIM_TYPES_H

74
SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_F072xB.h
View File

@@ -18,7 +18,7 @@
#define SHAL_UART4 UART(4)
//Valid usart Tx and Rx pairings for STM32F072
enum class UART_Pair : uint8_t{
enum class UART_Pair_Key : uint8_t{
//UART1
Tx1A9_Rx1A10,
Tx1B6_Rx1B7,
@@ -41,65 +41,65 @@ enum class UART_Pair : uint8_t{
};
constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){
constexpr SHAL_UART_Pair getUARTPair(const UART_Pair_Key pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10: return {USART1, GPIO_Key::A9, GPIO_Key::A10, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair::Tx1B6_Rx1B7: return {USART1, GPIO_Key::B6, GPIO_Key::B7, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
case UART_Pair::Tx2A2_Rx2A3: return {USART2, GPIO_Key::A2, GPIO_Key::A3, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair::Tx2A14_Rx2A15: return {USART2, GPIO_Key::A14, GPIO_Key::A15, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair::Tx3B10_Rx3B11: return {USART3, GPIO_Key::B10, GPIO_Key::B11, GPIO_Alternate_Function::AF4, GPIO_Alternate_Function::AF4};
case UART_Pair::Tx3C4_Rx3C5: return {USART3, GPIO_Key::C4, GPIO_Key::C5, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair::Tx3C10_Rx3C11: return {USART3, GPIO_Key::C10, GPIO_Key::C11, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair::Tx4A0_Rx4A1: return {USART4, GPIO_Key::A0, GPIO_Key::A1, GPIO_Alternate_Function::AF4, GPIO_Alternate_Function::AF4};
case UART_Pair::Tx4C10_Rx4C11: return {USART4, GPIO_Key::C10, GPIO_Key::C11, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
case UART_Pair_Key::Tx1A9_Rx1A10: return {USART1, GPIO_Key::A9, GPIO_Key::A10, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx1B6_Rx1B7: return {USART1, GPIO_Key::B6, GPIO_Key::B7, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
case UART_Pair_Key::Tx2A2_Rx2A3: return {USART2, GPIO_Key::A2, GPIO_Key::A3, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx2A14_Rx2A15: return {USART2, GPIO_Key::A14, GPIO_Key::A15, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx3B10_Rx3B11: return {USART3, GPIO_Key::B10, GPIO_Key::B11, GPIO_Alternate_Function::AF4, GPIO_Alternate_Function::AF4};
case UART_Pair_Key::Tx3C4_Rx3C5: return {USART3, GPIO_Key::C4, GPIO_Key::C5, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx3C10_Rx3C11: return {USART3, GPIO_Key::C10, GPIO_Key::C11, GPIO_Alternate_Function::AF1, GPIO_Alternate_Function::AF1};
case UART_Pair_Key::Tx4A0_Rx4A1: return {USART4, GPIO_Key::A0, GPIO_Key::A1, GPIO_Alternate_Function::AF4, GPIO_Alternate_Function::AF4};
case UART_Pair_Key::Tx4C10_Rx4C11: return {USART4, GPIO_Key::C10, GPIO_Key::C11, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr, GPIO_Key::INVALID, GPIO_Key::INVALID, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
}
__builtin_unreachable();
}
constexpr uint8_t getUARTChannel(const UART_Pair pair){
constexpr uint8_t getUARTChannel(const UART_Pair_Key pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10:
case UART_Pair::Tx1B6_Rx1B7:
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return 0;
case UART_Pair::Tx2A2_Rx2A3:
case UART_Pair::Tx2A14_Rx2A15:
case UART_Pair_Key::Tx2A2_Rx2A3:
case UART_Pair_Key::Tx2A14_Rx2A15:
return 1;
case UART_Pair::Tx3B10_Rx3B11:
case UART_Pair::Tx3C4_Rx3C5:
case UART_Pair::Tx3C10_Rx3C11:
case UART_Pair_Key::Tx3B10_Rx3B11:
case UART_Pair_Key::Tx3C4_Rx3C5:
case UART_Pair_Key::Tx3C10_Rx3C11:
return 2;
case UART_Pair::Tx4A0_Rx4A1:
case UART_Pair::Tx4C10_Rx4C11:
case UART_Pair_Key::Tx4A0_Rx4A1:
case UART_Pair_Key::Tx4C10_Rx4C11:
return 3;
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return 0;
}
__builtin_unreachable();
}
constexpr SHAL_UART_ENABLE_REG getUARTEnableReg(const UART_Pair pair){
constexpr SHAL_UART_Enable_Register getUARTEnableReg(const UART_Pair_Key pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10:
case UART_Pair::Tx1B6_Rx1B7:
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return {&RCC->APB2ENR,RCC_APB2ENR_USART1EN};
case UART_Pair::Tx2A2_Rx2A3:
case UART_Pair::Tx2A14_Rx2A15:
case UART_Pair_Key::Tx2A2_Rx2A3:
case UART_Pair_Key::Tx2A14_Rx2A15:
return {&RCC->APB1ENR,RCC_APB1ENR_USART2EN};
case UART_Pair::Tx3B10_Rx3B11:
case UART_Pair::Tx3C4_Rx3C5:
case UART_Pair::Tx3C10_Rx3C11:
case UART_Pair_Key::Tx3B10_Rx3B11:
case UART_Pair_Key::Tx3C4_Rx3C5:
case UART_Pair_Key::Tx3C10_Rx3C11:
return {&RCC->APB1ENR,RCC_APB1ENR_USART3EN};
case UART_Pair::Tx4A0_Rx4A1:
case UART_Pair::Tx4C10_Rx4C11:
case UART_Pair_Key::Tx4A0_Rx4A1:
case UART_Pair_Key::Tx4C10_Rx4C11:
return {&RCC->APB1ENR,RCC_APB1ENR_USART4EN};
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr, 0};
}

113
SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_H753ZI.h Normal file
View File

@@ -0,0 +1,113 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_UART_REG_F072XB_H
#define SHAL_UART_REG_F072XB_H
#include <stm32h753xx.h>
#include <cassert>
#include "SHAL_UART_TYPES.h"
#define NUM_USART_LINES 4
#define SHAL_UART1 UART(1)
#define SHAL_UART2 UART(2)
#define SHAL_UART3 UART(3)
#define SHAL_UART4 UART(4)
//Valid usart Tx and Rx pairings for STM32F072
enum class UART_Pair_Key : uint8_t{
//UART2
Tx2A2_Rx2A3,
Tx3D8_Rx3D9,
NUM_PAIRS,
INVALID
};
static SHAL_UART_Pair getUARTPair(const UART_Pair_Key pair){
switch(pair){
case UART_Pair_Key::Tx2A2_Rx2A3:
return {USART2, GPIO_Key::A2, GPIO_Key::A3, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::Tx3D8_Rx3D9:
return {USART3, GPIO_Key::D8, GPIO_Key::D9, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr, GPIO_Key::INVALID, GPIO_Key::INVALID, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
default:
__builtin_unreachable();
}
}
constexpr SHAL_UART_Enable_Register getUARTEnableReg(const UART_Pair_Key pair){
switch(pair){
case UART_Pair_Key::Tx2A2_Rx2A3:
return {&RCC->APB1LENR,RCC_APB1LENR_USART2EN};
case UART_Pair_Key::Tx3D8_Rx3D9:
return {&RCC->APB1LENR,RCC_APB1LENR_USART3EN};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
static SHAL_UART_Control_Register_1 getUARTControlRegister1(const UART_Pair_Key key) {
SHAL_UART_Control_Register_1 res = {
nullptr,
USART_CR1_UE,
USART_CR1_TE,
USART_CR1_RE,
USART_CR1_M0,
USART_CR1_M1,
USART_CR1_RXNEIE
};
res.reg = &getUARTPair(key).USARTReg->CR1;
return res;
};
static SHAL_UART_Baud_Rate_Generation_Register getUARTBaudRateRegister(const UART_Pair_Key key) {
SHAL_UART_Baud_Rate_Generation_Register res = {nullptr};
res.reg = &getUARTPair(key).USARTReg->BRR;
return res;
}
static SHAL_UART_ISR getUARTISR(const UART_Pair_Key key) { //TODO Support for multiple alternates for FIFO
SHAL_UART_ISR res = {
nullptr,
USART_ISR_TXE_TXFNF,
USART_ISR_TC,
USART_ISR_BUSY
};
res.reg = &getUARTPair(key).USARTReg->ISR;
return res;
}
static SHAL_UART_Transmit_Data_Register getUARTTransmitDataRegister(const UART_Pair_Key key) {
return {&getUARTPair(key).USARTReg->TDR};
}
static
constexpr uint32_t getAFMask(const GPIO_Alternate_Function mask){
switch(mask){
case GPIO_Alternate_Function::AF0: return 0x00;
case GPIO_Alternate_Function::AF1: return 0x01;
case GPIO_Alternate_Function::AF2: return 0x02;
case GPIO_Alternate_Function::AF3: return 0x03;
case GPIO_Alternate_Function::AF4: return 0x04;
case GPIO_Alternate_Function::AF5: return 0x05;
case GPIO_Alternate_Function::AF6: return 0x06;
case GPIO_Alternate_Function::AF7: return 0x07;
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_UART_REG_F072XB_H

104
SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_L432KC.h Normal file
View File

@@ -0,0 +1,104 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHAL_UART_REG_L432KC_H
#define SHAL_UART_REG_L432KC_H
#include <stm32l432xx.h>
#include <cassert>
#include "SHAL_UART_TYPES.h"
#define NUM_USART_LINES 4
#define SHAL_UART1 UART(1)
#define SHAL_UART2 UART(2)
//Valid usart Tx and Rx pairings for STM32L432KC
enum class UART_Pair_Key : uint8_t{
//UART1
Tx1A9_Rx1A10,
Tx1B6_Rx1B7,
//UART2
Tx2A2_Rx2A3,
NUM_PAIRS,
INVALID
};
static inline SHAL_UART_Pair getUARTPair(const UART_Pair_Key pair){
switch(pair){
case UART_Pair_Key::Tx1A9_Rx1A10: return {USART1, GPIO_Key::A9, GPIO_Key::A10, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::Tx1B6_Rx1B7: return {USART1, GPIO_Key::B6, GPIO_Key::B7, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::Tx2A2_Rx2A3: return {USART2, GPIO_Key::A2, GPIO_Key::A3, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
__builtin_unreachable();
}
__builtin_unreachable();
}
static inline uint8_t getUARTChannel(const UART_Pair_Key pair){ //TODO remove?
switch(pair){
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return 0;
case UART_Pair_Key::Tx2A2_Rx2A3:
return 1;
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return 0;
}
__builtin_unreachable();
}
constexpr SHAL_UART_Enable_Register getUARTEnableReg(const UART_Pair_Key pair){
switch(pair){
case UART_Pair_Key::Tx1A9_Rx1A10:
case UART_Pair_Key::Tx1B6_Rx1B7:
return {&RCC->APB2ENR,RCC_APB2ENR_USART1EN};
case UART_Pair_Key::Tx2A2_Rx2A3:
return {&RCC->APB1ENR1,RCC_APB1ENR1_USART2EN};
case UART_Pair_Key::NUM_PAIRS:
case UART_Pair_Key::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
static inline SHAL_UART_Control_Register_1 getUARTControlRegister1(UART_Pair_Key key){
SHAL_UART_Control_Register_1 res = {nullptr, USART_CR1_UE, USART_CR1_TE, USART_CR1_RE};
res.reg = &getUARTPair(key).USARTReg->CR1;
return res;
};
static inline SHAL_UART_Baud_Rate_Generation_Register getUARTBaudRateGenerationRegister(UART_Pair_Key key){
SHAL_UART_Baud_Rate_Generation_Register res = {nullptr}; //TODO un-hardcode if other devices have wider baud rate allowances
res.reg = &getUARTPair(key).USARTReg->BRR;
return res;
};
static inline SHAL_UART_Transmit_Data_Register getUARTTransmitDataRegister(UART_Pair_Key key){
SHAL_UART_Transmit_Data_Register res = {nullptr}; //TODO un-hardcode if other devices have wider baud rate allowances
res.reg = &getUARTPair(key).USARTReg->TDR;
return res;
};
static inline SHAL_UART_ISR_FIFO_Disabled getUARTISRFifoDisabled(UART_Pair_Key key){
SHAL_UART_ISR_FIFO_Disabled res = {nullptr, USART_ISR_TXE};
res.reg = &getUARTPair(key).USARTReg->ISR;
return res;
};
#endif //SHAL_UART_REG_F072XB_H

12
SHAL/Include/Peripheral/UART/SHAL_UART.h
View File

@@ -10,22 +10,22 @@
#define SHMINGO_HAL_SHAL_UART_H
#include "SHAL_UART_REG.h"
#include "SHAL_UART_TYPES.h"
class SHAL_UART{
friend class UARTManager;
public:
void init(UART_Pair pair);
void init(UART_Pair_Key pair);
//begins Tx and Usart TODO either modify this function or add a new one that supports Rx
void begin(uint32_t baudRate) volatile;
void begin(uint32_t baudRate, SHAL_USART_Word_Length wordLength) const volatile;
//Sends a string
void sendString(const char* s) volatile;
void sendString(const char* s) const volatile;
//Sends a char
void sendChar(char c) volatile;
void sendChar(char c) const volatile;
private:
@@ -33,7 +33,7 @@ private:
//Creates a SHAL_UART based on a pair of two valid U(S)ART pins
UART_Pair m_UARTPair = UART_Pair::INVALID;
UART_Pair_Key m_key = UART_Pair_Key::INVALID;
};

47
SHAL/Include/Peripheral/UART/SHAL_UART_REG.h
View File

@@ -47,7 +47,7 @@
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#include "SHAL_UART_REG_L432KC.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
@@ -89,7 +89,52 @@
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#elif defined(STM32H743xx)
#include "stm32h743xx.h"
#elif defined(STM32H753xx)
#include "SHAL_UART_REG_H753ZI.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H745xG)
#include "stm32h745xg.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H747xG)
#include "stm32h747xg.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#elif defined(STM32H735xx)
#include "stm32h735xx.h"
#elif defined(STM32H733xx)
#include "stm32h733xx.h"
#elif defined(STM32H730xx)
#include "stm32h730xx.h"
#elif defined(STM32H730xxQ)
#include "stm32h730xxq.h"
#elif defined(STM32H725xx)
#include "stm32h725xx.h"
#elif defined(STM32H723xx)
#include "stm32h723xx.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

38
SHAL/Include/Peripheral/UART/SHAL_UART_TYPES.h
View File

@@ -8,8 +8,6 @@
#include "SHAL_CORE.h"
#include "SHAL_GPIO_REG.h"
//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping
struct SHAL_UART_Pair{
USART_TypeDef* USARTReg;
@@ -19,9 +17,43 @@ struct SHAL_UART_Pair{
GPIO_Alternate_Function RxAlternateFunctionMask;
};
struct SHAL_UART_ENABLE_REG{
struct SHAL_UART_Enable_Register{
volatile uint32_t* reg;
uint32_t mask;
};
struct SHAL_UART_Control_Register_1 {
volatile uint32_t* reg;
uint32_t usart_enable_mask;
uint32_t transmit_enable_mask;
uint32_t receive_enable_mask;
uint32_t m0_mask;
uint32_t m1_mask;
uint32_t Rx_interrupt_enable_mask;
};
struct SHAL_UART_Baud_Rate_Generation_Register {
volatile uint32_t* reg;
};
struct SHAL_UART_ISR {
volatile uint32_t* reg;
uint32_t transmit_data_register_empty_mask;
uint32_t transmission_complete_mask;
uint32_t busy_mask;
};
struct SHAL_UART_Transmit_Data_Register {
volatile uint32_t* reg;
};
enum class SHAL_USART_Word_Length : uint32_t { //See M bits for USART
Bits_7 = 1 << 28,
Bits_8 = 0,
Bits_9 = 1 << 12 //Universal M bit implementation
};
#endif //SHMINGO_HAL_SHAL_UART_TYPES_H

4
SHAL/Include/SHAL.h
View File

@@ -10,10 +10,6 @@
#include "SHAL_TIM.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART.h"
#include "SHAL_I2C.h"
#include "SHAL_ADC.h"
#endif

128
SHAL/Src/STM32F0XX/Peripheral/GPIO/SHAL_GPIO.cpp
View File

@@ -1,128 +0,0 @@
//
// Created by Luca on 8/30/2025.
//
#include "SHAL_GPIO.h"
#include "SHAL_EXTI_CALLBACK.h"
SHAL_GPIO::SHAL_GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
volatile unsigned long* gpioEnable = getGPIORCCEnable(key).reg;
unsigned long gpioOffset = getGPIORCCEnable(key).offset;
*gpioEnable |= (1 << gpioOffset); //Set enable flag
}
void SHAL_GPIO::setLow() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR &= ~(1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setHigh() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR |= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::toggle() volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR ^= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setPinType(PinType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OTYPER &= ~(1 << gpioPeripheral.global_offset);
gpioPeripheral.reg->OTYPER |= (static_cast<uint8_t>(type) << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OSPEEDR |= (static_cast<uint8_t>(speed) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setInternalResistor(InternalResistorType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->PUPDR &= ~(0x03 << (2 * gpioPeripheral.global_offset));
gpioPeripheral.reg->PUPDR |= (static_cast<uint8_t>(type) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
int afrIndex = gpioPeripheral.global_offset < 8 ? 0 : 1; //Get index of AFR
gpioPeripheral.reg->AFR[afrIndex] &= ~(0xF << (gpioPeripheral.global_offset * 4));
gpioPeripheral.reg->AFR[afrIndex] |= (static_cast<int>(AF) << (gpioPeripheral.global_offset * 4));
}
void SHAL_GPIO::setPinMode(PinMode mode) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->MODER &= ~(0x03 << (2 * gpioPeripheral.global_offset)); //Clear any previous mode
gpioPeripheral.reg->MODER |= (static_cast<uint8_t>(mode) << (2 * gpioPeripheral.global_offset)); //Set mode based on pinmode bit structure
}
void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {
uint32_t gpioPin = getGPIORegister(m_GPIO_KEY).global_offset; //Use existing structs to get offset
setPinMode(PinMode::INPUT_MODE); //Explicitly set mode to input
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; //Enable EXT, TODO check if this is different across STM32 models
NVIC_EnableIRQ(getGPIOEXTICR(m_GPIO_KEY).IRQN); //Enable IRQN for pin
EXTI->IMR |= (1 << gpioPin); //Enable correct EXTI line
SHAL_EXTIO_Register EXTILineEnable = getGPIOEXTICR(m_GPIO_KEY);
*EXTILineEnable.EXT_ICR |= EXTILineEnable.mask; //Set bits to enable correct port on correct line TODO Find way to clear bits before
uint32_t rising_mask = 0x00;
uint32_t falling_mask = 0x00;
//Set rising and falling edge triggers based on pin offset (enabled EXTI line)
switch(mode){
case TriggerMode::RISING_EDGE:
rising_mask = 1 << gpioPin;
break;
case TriggerMode::FALLING_EDGE:
falling_mask = 1 << gpioPin;
break;
case TriggerMode::RISING_FALLING_EDGE:
falling_mask = 1 << gpioPin;
falling_mask = 1 << gpioPin;
}
//Set triggers
EXTI->RTSR |= rising_mask;
EXTI->FTSR |= falling_mask;
//Set callback
registerEXTICallback(m_GPIO_KEY,callback);
__enable_irq(); //Enable IRQ just in case
}
uint16_t SHAL_GPIO::analogRead(ADC_SampleTime sampleTime) {
SHAL_ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
}
SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
unsigned int gpioPort = getGPIOPortNumber(key);
unsigned long gpioPin = getGPIORegister(key).global_offset; //Use existing structs to get offset
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
}
return m_gpios[gpioPort][gpioPin];
}

63
SHAL/Src/STM32F0XX/Peripheral/Timer/SHAL_TIM.cpp
View File

@@ -1,63 +0,0 @@
//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM.h"
#include <cassert>
Timer::Timer(Timer_Key t) : TIMER_KEY(t){
}
Timer::Timer() : TIMER_KEY(Timer_Key::S_TIM_INVALID){
}
void Timer::start() {
getTimerRegister(TIMER_KEY)->CR1 |= TIM_CR1_CEN;
getTimerRegister(TIMER_KEY)->EGR |= TIM_EGR_UG; //load prescaler reg and ARR
enableInterrupt();
}
void Timer::stop() {
getTimerRegister(TIMER_KEY)->CR1 &= ~TIM_CR1_CEN;
}
void Timer::setPrescaler(uint16_t presc) {
getTimerRegister(TIMER_KEY)->PSC = presc;
}
void Timer::setARR(uint16_t arr) {
getTimerRegister(TIMER_KEY)->ARR = arr;
}
void Timer::enableInterrupt() {
getTimerRegister(TIMER_KEY)->DIER |= TIM_DIER_UIE;
NVIC_EnableIRQ(getIRQn(TIMER_KEY));
}
void Timer::init(uint32_t prescaler, uint32_t autoReload) {
TIM_RCC_Enable rcc = getTimerRCC(TIMER_KEY);
*rcc.busEnableReg |= (1 << rcc.offset);
setPrescaler(prescaler);
setARR(autoReload);
}
Timer &TimerManager::get(Timer_Key timer_key) {
//Ensure that we don't try to get invalid timers
assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
Timer& selected = timers[static_cast<int>(timer_key)];
//Timer queried is not initialized yet (defaults to invalid)
if(selected.TIMER_KEY == Timer_Key::S_TIM_INVALID){
timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
}
return timers[static_cast<int>(timer_key)];
}

7
SHAL/Src/STM32F0XX/Core/SHAL_CORE.cpp → SHAL/Src/STM32F0xx/Core/SHAL_CORE.cpp
View File

@@ -16,6 +16,13 @@ void systick_init(){
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
}
extern "C" void SysTick_Handler() {
ticks++;
}
static uint32_t millis();
void SHAL_delay_us(uint32_t us){
uint32_t ticks = us * (SystemCoreClock / 1000000U);

0
SHAL/Src/STM32F0XX/EXT/SHAL_EXTI_CALLBACK.cpp → SHAL/Src/STM32F0xx/EXT/SHAL_EXTI_CALLBACK.cpp
View File

6
SHAL/Src/STM32F0XX/Peripheral/ADC/SHAL_ADC.cpp → SHAL/Src/STM32F0xx/Peripheral/ADC/SHAL_ADC.cpp
View File

@@ -5,7 +5,7 @@
#include "SHAL_ADC.h"
//Can hard code registers on F0 because all F0 devices have only one ADC, and use only one clock
SHAL_Result SHAL_ADC::init() {
SHAL_Result SHAL_ADC::init(ADC_Key key) {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return SHAL_Result::ERROR;
@@ -64,7 +64,7 @@ SHAL_Result SHAL_ADC::calibrate() {
return SHAL_Result::OKAY;
}
uint16_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, ADC_SampleTime time) {
uint16_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
@@ -81,7 +81,7 @@ uint16_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, ADC_SampleTime
return result;
}
void SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, const int numChannels, uint16_t* result, ADC_SampleTime time) {
SHAL_Result SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_TSEN; //Enable VREFINT and Temp sensor in global ADC struct

132
SHAL/Src/STM32F0xx/Peripheral/GPIO/SHAL_GPIO.cpp Normal file
View File

@@ -0,0 +1,132 @@
//
// Created by Luca on 8/30/2025.
//
#include "SHAL_GPIO.h"
//#include "SHAL_EXTI_CALLBACK.h"
SHAL_GPIO::SHAL_GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
auto GPIORCCEnable = getGPIORCCEnable(key);
SHAL_set_register_value(GPIORCCEnable.reg,GPIORCCEnable.mask);
}
void SHAL_GPIO::setLow() const {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_set_bits(outputDataReg.reg,1,0,outputDataReg.offset);
}
void SHAL_GPIO::setHigh() const {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_set_bits(outputDataReg.reg,1,1,outputDataReg.offset);
}
void SHAL_GPIO::toggle() const volatile {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_flip_bits(outputDataReg.reg,1,outputDataReg.offset);
}
void SHAL_GPIO::setOutputType(PinType type) const volatile {
auto outputTypeReg = getGPIOOutputTypeRegister(m_GPIO_KEY);
SHAL_set_bits(outputTypeReg.reg,2,static_cast<uint8_t>(type),outputTypeReg.offset);
}
void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) const volatile {
auto outputSpeedReg = getGPIOOutputSpeedRegister(m_GPIO_KEY);
SHAL_set_bits(outputSpeedReg.reg,2,static_cast<uint8_t>(speed),outputSpeedReg.offset);
}
void SHAL_GPIO::setInternalResistor(InternalResistorType type) const volatile {
auto pupdreg = getGPIOPUPDRegister(m_GPIO_KEY);
SHAL_set_bits(pupdreg.reg,2,static_cast<uint8_t>(type),pupdreg.offset);
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) const volatile {
auto alternateFunctionReg = getGPIOAlternateFunctionRegister(m_GPIO_KEY);
SHAL_set_bits(alternateFunctionReg.reg,4,static_cast<uint8_t>(AF),alternateFunctionReg.offset);
}
SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) const volatile {
auto pinModeReg = getGPIOModeRegister(m_GPIO_KEY);
/*
if(mode == PinMode::ANALOG_MODE && getGPIOPortInfo(m_GPIO_KEY).ADCChannel == SHAL_ADC_Channel::NO_ADC_MAPPING){
char buff[100];
sprintf(buff, "Error: GPIO pin %d has no valid ADC mapping\r\n", static_cast<uint8_t>(m_GPIO_KEY));
SHAL_UART2.sendString(buff);
return SHAL_Result::ERROR;
}
*/
SHAL_set_bits(pinModeReg.reg,2,static_cast<uint8_t>(mode),pinModeReg.offset); //Set mode
return SHAL_Result::OKAY;
}
/* TODO Fix implementation for STM32F072
void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {
uint32_t gpioPin = getGPIORegister(m_GPIO_KEY).global_offset; //Use existing structs to get offset
setPinMode(PinMode::INPUT_MODE); //Explicitly set mode to input
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; //Enable EXT, TODO check if this is different across STM32 models
NVIC_EnableIRQ(getGPIOEXTICR(m_GPIO_KEY).IRQN); //Enable IRQN for pin
EXTI->IMR |= (1 << gpioPin); //Enable correct EXTI line
SHAL_EXTIO_Register EXTILineEnable = getGPIOEXTICR(m_GPIO_KEY);
*EXTILineEnable.EXT_ICR |= EXTILineEnable.mask; //Set bits to enable correct port on correct line TODO Find way to clear bits before
uint32_t rising_mask = 0x00;
uint32_t falling_mask = 0x00;
//Set rising and falling edge triggers based on pin offset (enabled EXTI line)
switch(mode){
case TriggerMode::RISING_EDGE:
rising_mask = 1 << gpioPin;
break;
case TriggerMode::FALLING_EDGE:
falling_mask = 1 << gpioPin;
break;
case TriggerMode::RISING_FALLING_EDGE:
falling_mask = 1 << gpioPin;
falling_mask = 1 << gpioPin;
}
//Set triggers
EXTI->RTSR |= rising_mask;
EXTI->FTSR |= falling_mask;
//Set callback
registerEXTICallback(m_GPIO_KEY,callback);
__enable_irq(); //Enable IRQ just in case
}
*/
/* TODO reimplement
uint16_t SHAL_GPIO::analogRead(SHAL_ADC_SampleTime sampleTime) {
SHAL_ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
}
*/
SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
unsigned int gpioPort = getGPIOPortNumber(key);
uint8_t gpioPin = getGPIOPinNumber(key);
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
}
return m_gpios[gpioPort][gpioPin];
}

6
SHAL/Src/STM32L4XX/Peripheral/I2C/SHAL_I2C.cpp → SHAL/Src/STM32F0xx/Peripheral/I2C/SHAL_I2C.cpp
View File

@@ -27,8 +27,8 @@ void SHAL_I2C::init(I2C_Pair pair) volatile {
GET_GPIO(SDA_Key).setAlternateFunction(I2CPair.SDA_Mask);
//These may be abstracted further to support multiple I2C configurations
GET_GPIO(SCL_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SDA_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SCL_Key).setOutputType(PinType::OPEN_DRAIN);
GET_GPIO(SDA_Key).setOutputType(PinType::OPEN_DRAIN);
GET_GPIO(SCL_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
GET_GPIO(SDA_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
@@ -95,8 +95,6 @@ void SHAL_I2C::masterWriteRead(uint8_t addr,const uint8_t* writeData, size_t wri
//Read phase
if (readLen > 0) {
SHAL_UART2.sendString("Read initiated\r\n");
I2CPeripheral->CR2 &= ~(I2C_CR2_NBYTES | I2C_CR2_SADD | I2C_CR2_RD_WRN);
I2CPeripheral->CR2 |= (addr << 1) |
I2C_CR2_RD_WRN |

137
SHAL/Src/STM32F0xx/Peripheral/Timer/SHAL_TIM.cpp Normal file
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@@ -0,0 +1,137 @@
//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM.h"
#include <cassert>
Timer::Timer(Timer_Key t) : m_key(t){
}
Timer::Timer() : m_key(Timer_Key::S_TIM_INVALID){
}
void Timer::start() {
auto control_reg = getTimerControlRegister1(m_key);
auto event_generation_reg = getTimerEventGenerationRegister(m_key);
auto status_reg = getTimerStatusRegister(m_key);
auto break_time_dead_reg = getTimerBreakDeadTimeRegister(m_key);
auto rcc_reg = getTimerRCC(m_key);
SHAL_apply_bitmask(control_reg.reg, control_reg.counter_enable_mask); //Enable counter
SHAL_apply_bitmask(control_reg.reg, control_reg.auto_reload_preload_enable_mask); //Preload enable (buffer)
SHAL_apply_bitmask(event_generation_reg.reg, event_generation_reg.update_generation_mask);
SHAL_clear_bitmask(status_reg.reg,status_reg.update_interrupt_flag_mask);
SHAL_apply_bitmask(rcc_reg.reg,rcc_reg.enable_mask);
SHAL_apply_bitmask(break_time_dead_reg.reg,break_time_dead_reg.main_output_enable_mask);
enableInterrupt();
}
void Timer::stop() const {
auto rcc_reg = getTimerRCC(m_key);
SHAL_clear_bitmask(rcc_reg.reg,rcc_reg.enable_mask);
}
void Timer::setPrescaler(const uint32_t presc) const {
auto prescalerReg = getTimerPrescalerRegister(m_key);
SHAL_set_bits(prescalerReg.reg,16,presc,0);
}
void Timer::setARR(const uint32_t arr) const {
auto autoReloadReg = getTimerAutoReloadRegister(m_key);
SHAL_set_bits(autoReloadReg.reg,16,arr,0);}
void Timer::enableInterrupt() {
getTimerRegister(m_key)->DIER |= TIM_DIER_UIE;
NVIC_EnableIRQ(getIRQn(m_key));
}
void Timer::init(uint32_t prescaler, uint32_t autoReload) {
SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);
SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
setPrescaler(prescaler);
setARR(autoReload);
}
void Timer::configurePWM(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {
setPrescaler(prescaler);
setARR(autoReload);
setOutputCompareMode(channel, SHAL_TIM_Output_Compare_Mode::PWMMode1);
enableChannel(channel,SHAL_Timer_Channel_Main_Output_Mode::Polarity_Normal,SHAL_Timer_Channel_Complimentary_Output_Mode::Disabled);
setCaptureCompareValue(channel, captureCompareThreshold);
}
void Timer::configureOneshot(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {
setPrescaler(prescaler);
setARR(autoReload);
setOutputCompareMode(channel, SHAL_TIM_Output_Compare_Mode::Toggle);
enableChannel(channel,SHAL_Timer_Channel_Main_Output_Mode::Polarity_Normal,SHAL_Timer_Channel_Complimentary_Output_Mode::Disabled);
setCaptureCompareValue(channel, captureCompareThreshold);
}
void Timer::setOutputCompareMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode) const {
auto channelNum = static_cast<uint8_t>(channel);
auto CCMR = getTimerOutputCaptureCompareModeRegister(m_key, channel);
uint32_t OCMR_Offset = channelNum % 2 == 1 ? CCMR.output_compare_1_mode_offset : CCMR.output_compare_2_mode_offset;
SHAL_set_bits(CCMR.reg,3,static_cast<uint8_t>(outputCompareMode),OCMR_Offset);
}
void Timer::enableChannel(SHAL_Timer_Channel channel, SHAL_Timer_Channel_Main_Output_Mode mainOutputMode,
SHAL_Timer_Channel_Complimentary_Output_Mode complimentaryOutputMode) {
SHAL_TIM_Capture_Compare_Enable_Register captureCompareEnableReg = getTimerCaptureCompareEnableRegister(m_key, channel);
uint16_t setValue = 0; //Value to set the register as
auto channelNum = static_cast<uint8_t>(channel);
uint8_t channelStride = 4; //4 bits per field
setValue |= (static_cast<uint8_t>(mainOutputMode) << ((channelNum - 1) * channelStride)); //xxBB shifted by c - 1
setValue |= (static_cast<uint8_t>(complimentaryOutputMode) << (((channelNum - 1) * channelStride) + 2)); //BBxx shifted by c - 1
SHAL_set_bits(captureCompareEnableReg.reg,16,setValue,0);
}
void Timer::setCaptureCompareValue(SHAL_Timer_Channel channel, uint32_t value) const {
auto captureCompareReg = getTimerCaptureCompareRegister(m_key,channel);
SHAL_set_bits(captureCompareReg.reg,16,value,0);
}
Timer &TimerManager::get(Timer_Key timer_key) {
//Ensure that we don't try to get invalid timers
assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
Timer& selected = timers[static_cast<int>(timer_key)];
//Timer queried is not initialized yet (defaults to invalid)
if(selected.m_key == Timer_Key::S_TIM_INVALID){
timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
}
return timers[static_cast<int>(timer_key)];
}

0
SHAL/Src/STM32F0XX/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp → SHAL/Src/STM32F0xx/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp
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4
SHAL/Src/STM32L4XX/Peripheral/UART/SHAL_UART.cpp → SHAL/Src/STM32F0xx/Peripheral/UART/SHAL_UART.cpp
View File

@@ -10,7 +10,7 @@
#include "SHAL_UART.h"
#include "SHAL_GPIO.h"
void SHAL_UART::init(const UART_Pair pair){
void SHAL_UART::init(const UART_Pair_Key pair){
m_UARTPair = pair;
@@ -26,7 +26,7 @@ void SHAL_UART::init(const UART_Pair pair){
GET_GPIO(Tx_Key).setAlternateFunction(uart_pair.TxAlternateFunctionMask);
GET_GPIO(Rx_Key).setAlternateFunction(uart_pair.RxAlternateFunctionMask);
SHAL_UART_ENABLE_REG pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the SHAL_UART channel
SHAL_UART_Enable_Register pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the SHAL_UART channel
*pairUARTEnable.reg |= pairUARTEnable.mask; //Enable SHAL_UART line

0
SHAL/Src/STM32F0XX/System/system_stm32f0xx.c → SHAL/Src/STM32F0xx/System/system_stm32f0xx.c
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90
SHAL/Src/STM32H7xx/Core/SHAL_CORE.cpp Normal file
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@@ -0,0 +1,90 @@
//
// Created by Luca on 9/15/2025.
//
#include "SHAL_CORE.h"
#include <cassert>
void SHAL_init(){
systick_init(); //Just this for now
SystemInit();
PWR->CR3 |= PWR_CR3_LDOEN; //TODO don't hardcode
SHAL_WAIT_FOR_CONDITION_US(((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) != 0),500);
}
void systick_init(){
SysTick->CTRL = 0; //Disable first
SysTick->LOAD = 0xFFFFFF; //Max 24-bit
SysTick->VAL = 0; //Clear
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
}
extern "C" void SysTick_Handler() {
ticks++;
}
static uint32_t millis();
void SHAL_delay_us(uint32_t us){
uint32_t ticks = us * (SystemCoreClock / 1000000U);
uint32_t start = SysTick->VAL;
//Calculate target value (may wrap around)
uint32_t target = (start >= ticks) ? (start - ticks) : (start + 0x01000000 - ticks);
target &= 0x00FFFFFF;
//Wait until we reach the target
if (start >= ticks) {
//No wraparound case
while (SysTick->VAL > target) {}
} else {
while (SysTick->VAL <= start) {} //Wait for wraparound
while (SysTick->VAL > target) {} //Wait for target
}
}
void SHAL_delay_ms(uint32_t ms){
while(ms-- > 0){
SHAL_delay_us(1000);
}
}
bool SHAL_wait_for_bit_set_us(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
if(SHAL_WAIT_FOR_CONDITION_US((*reg & mask) != 0, timeout)){
return true;
}
return false;
}
bool SHAL_wait_for_bit_clear_us(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
if(SHAL_WAIT_FOR_CONDITION_US((*reg & mask) == 0, timeout)){
return true;
}
return false;
}
bool SHAL_wait_for_bit_set_ms(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
if(SHAL_WAIT_FOR_CONDITION_MS((*reg & mask) != 0, timeout)){
return true;
}
return false;
}
bool SHAL_wait_for_bit_clear_ms(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
if(SHAL_WAIT_FOR_CONDITION_MS((*reg & mask) == 0, timeout)){
return true;
}
return false;
}
bool SHAL_check_bit(const volatile uint32_t* reg, const uint32_t mask) {
if ((*reg & mask) != 0) return true;
return false;
}

271
SHAL/Src/STM32H7xx/Peripheral/ADC/SHAL_ADC.cpp Normal file
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@@ -0,0 +1,271 @@
//
// Created by Luca on 9/21/2025.
//
#include "SHAL_ADC.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART.h"
#include <cstdio>
bool SHAL_ADC::isValid() const {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return false;
}
return true;
}
SHAL_Result SHAL_ADC::init(const ADC_Key key, SHAL_ADC_Sample_Mode mode){
m_ADCKey = key;
if(!isValid()){
return SHAL_Result::ERROR;
}
auto rcc = getADCRCCEnableRegister(m_ADCKey); //Clock enable
auto ccr = getADCCommonControl(m_ADCKey);
SHAL_apply_bitmask(rcc.reg,rcc.mask); //Enable clock
wakeFromDeepSleep(); //Wake and enable LDO
//Configure clock source
SHAL_set_bits(ccr.reg,2,static_cast<uint32_t>(SHAL_ADC_Clock_Mode::SYNC_BY_2),ccr.clock_mode_position); //TODO take as param?
configureResolution(SHAL_ADC_Resolution::B12); //Configure resolution
SHAL_apply_bitmask(ccr.reg,ccr.VoltageRefEnable);
if(calibrate(mode) != SHAL_Result::OKAY){ //Calibrate
return SHAL_Result::ERROR;
}
if(enable() != SHAL_Result::OKAY){
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::calibrate(SHAL_ADC_Sample_Mode sampleMode) const {
const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
if(disable() != SHAL_Result::OKAY){
return SHAL_Result::ERROR;
}
SHAL_set_bits(control_reg.reg, 1, static_cast<uint32_t>(sampleMode), control_reg.sample_mode_offset); //Set sample mode (differential or single ended)
SHAL_apply_bitmask(control_reg.reg, control_reg.calibration_mask); //Start calibration
if (!SHAL_wait_for_bit_clear_us(control_reg.reg, control_reg.calibration_mask, 100)) { //Wait for calibration
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
uint32_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time) const {
auto data_reg = getADCDataReg(m_ADCKey);
auto ISR_reg = getADCISRReg(m_ADCKey);
auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey, channel);
SHAL_set_bits(sampleTimeReg.reg, 3, static_cast<uint8_t>(time), sampleTimeReg.channel_offset); //Set sample time
if(setADCSequenceAmount(1) == SHAL_Result::ERROR) { return 0; } //Set sequence amount to 1
addADCChannelToSequence(channel, 1);
startConversion();
if (!SHAL_wait_for_bit_set_us(ISR_reg.reg, ISR_reg.end_of_conversion_mask, 200)) {
return 0;
}
uint32_t result = *data_reg.reg;
return result;
}
SHAL_Result SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time) {
auto data_reg = getADCDataReg(m_ADCKey); //Where our output will be stored
setADCSequenceAmount(numChannels); //Convert the correct amount of channels
for(int i = 0; i < numChannels; i++){
auto channel = channels[i];
auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey,channel);
SHAL_set_bits(sampleTimeReg.reg,3,static_cast<uint8_t>(time),sampleTimeReg.channel_offset); //Set sample time register TODO un-hardcode bit width?
addADCChannelToSequence(channel,i); //Use index 0 to convert channel
}
startConversion(); //Start ADC conversion
auto ISR_reg = getADCISRReg(m_ADCKey);
for(int i = 0; i < numChannels; i++) {
if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_conversion_mask) != 0),500)) { //Wait for conversion
return SHAL_Result::ERROR; //Failed conversion
}
result[i] = *data_reg.reg;
}
if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_sequence_mask) != 0),500)) { //Wait for conversion
return SHAL_Result::ERROR; //Failed sequence
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::enable() const {
if(!isValid()){
return SHAL_Result::ERROR;
}
const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
const SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask); //Clear ready flag (write is correct as per datasheet)
SHAL_apply_bitmask(control_reg.reg, control_reg.enable_mask); //Enable mask
if (!SHAL_wait_for_bit_set_us(ISR_reg.reg,ISR_reg.ready_mask,500)) { //Check ADRDY
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
/// Disables the ADC
/// @return
SHAL_Result SHAL_ADC::disable() const {
if(!isValid()){
return SHAL_Result::ERROR;
}
const auto control_reg = getADCControlReg(m_ADCKey);
//Stop any ongoing conversion
if (SHAL_check_bit(control_reg.reg, control_reg.start_mask)) {
SHAL_apply_bitmask(control_reg.reg, control_reg.stop_mask);
}
if (SHAL_check_bit(control_reg.reg,control_reg.enable_mask)) { //DO NOT disable if the ADC is already disabled
SHAL_apply_bitmask(control_reg.reg, control_reg.disable_mask);
if (!SHAL_wait_for_bit_clear_ms(control_reg.reg,(control_reg.enable_mask | control_reg.disable_mask),50)) {
return SHAL_Result::ERROR;
}
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::wakeFromDeepSleep() const {
const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey); //ADC Control register
const SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
SHAL_clear_bitmask(control_reg.reg,control_reg.deep_power_down_mask); //Wake ADC from sleep
SHAL_apply_bitmask(control_reg.reg,control_reg.voltage_regulator_mask);
if (!SHAL_wait_for_bit_set_us(ISR_reg.reg,ISR_reg.ldo_ready_mask,50)) { //Wait for LDO
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::startConversion() const {
auto control_reg = getADCControlReg(m_ADCKey);
SHAL_apply_bitmask(control_reg.reg,control_reg.start_mask);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::configureResolution(SHAL_ADC_Resolution resolution) const {
if(!isValid()){
return SHAL_Result::ERROR;
}
const SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
/*
SHAL_set_bits(config_reg.reg,2,static_cast<uint8_t>(resolution),config_reg.resolution_offset);
char buff[20];
snprintf(buff,16,"CFGR: %lu\r\n", (unsigned long)ADC1->CFGR);
SHAL_UART3.sendString(buff);
*/
SHAL_set_register_value(config_reg.reg, 0);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::configureAlignment(SHAL_ADC_Alignment alignment) const {
if(!isValid()){
return SHAL_Result::ERROR;
}
const SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
//TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
SHAL_set_bits(config_reg.reg,1,static_cast<uint8_t>(alignment),config_reg.alignment_offset);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::preselectChannel(SHAL_ADC_Channel channel) const {
auto preselect = getADCPreselectRegister(ADC_Key::S_ADC1, SHAL_ADC_Channel::CH15);
SHAL_set_bits(preselect.reg,1,1,preselect.channel_offset);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::setADCSequenceAmount(uint32_t amount) const {
if(!isValid()){return SHAL_Result::ERROR;}
if(amount == 0){
return SHAL_Result::ERROR;
}
SHAL_ADC_Sequence_Amount_Reg sequence_amount_reg = getADCSequenceAmountRegister(m_ADCKey);
SHAL_set_bits(sequence_amount_reg.reg, 4, amount - 1, 0); //Sequence amount reg is just SQR1 least significant 4 bits, this offset should always be 0
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::addADCChannelToSequence(SHAL_ADC_Channel channel, const uint32_t conversionNumber) const {
if(!isValid()) { return SHAL_Result::ERROR; }
auto sqr = getADCSequenceRegister(m_ADCKey, conversionNumber);
auto channelNum = static_cast<uint8_t>(channel);
SHAL_wait_for_bit_clear_ms(&ADC1->CR,ADC_CR_ADSTART,50);
SHAL_set_bits(sqr.reg, 5, channelNum, sqr.sequence_offset); //Set regular sequence register
return SHAL_Result::OKAY;
}
SHAL_ADC &ADCManager::get(ADC_Key key) {
return m_ADCs[static_cast<uint8_t>(key)];
}
SHAL_ADC& ADCManager::getByIndex(int index) {
if(index < static_cast<int>(ADC_Key::NUM_ADC)){
return m_ADCs[index];
}
return m_ADCs[0];
}

156
SHAL/Src/STM32H7xx/Peripheral/GPIO/SHAL_GPIO.cpp Normal file
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@@ -0,0 +1,156 @@
//
// Created by Luca on 8/30/2025.
//
#include "SHAL_GPIO.h"
//#include "SHAL_EXTI_CALLBACK.h"
SHAL_GPIO::SHAL_GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
auto GPIORCCEnable = getGPIORCCEnable(key);
SHAL_apply_bitmask(GPIORCCEnable.reg,GPIORCCEnable.mask);
}
void SHAL_GPIO::setLow() const {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_set_bits(outputDataReg.reg,1,0,outputDataReg.offset);
}
void SHAL_GPIO::setHigh() const {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_set_bits(outputDataReg.reg,1,1,outputDataReg.offset);
}
void SHAL_GPIO::toggle() const volatile {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_flip_bits(outputDataReg.reg,1,outputDataReg.offset);
}
void SHAL_GPIO::setOutputType(PinType type) const volatile {
auto outputTypeReg = getGPIOOutputTypeRegister(m_GPIO_KEY);
SHAL_set_bits(outputTypeReg.reg,2,static_cast<uint8_t>(type),outputTypeReg.offset);
}
void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) const volatile {
auto outputSpeedReg = getGPIOOutputSpeedRegister(m_GPIO_KEY);
SHAL_set_bits(outputSpeedReg.reg,2,static_cast<uint8_t>(speed),outputSpeedReg.offset);
}
void SHAL_GPIO::setInternalResistor(InternalResistorType type) const volatile {
auto pupdreg = getGPIOPUPDRegister(m_GPIO_KEY);
SHAL_set_bits(pupdreg.reg,2,static_cast<uint8_t>(type),pupdreg.offset);
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) const volatile {
auto alternateFunctionReg = getGPIOAlternateFunctionRegister(m_GPIO_KEY);
SHAL_set_bits(alternateFunctionReg.reg,4,static_cast<uint8_t>(AF),alternateFunctionReg.offset);
}
SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) const volatile {
auto pinModeReg = getGPIOModeRegister(m_GPIO_KEY);
GPIOManager::initGPIO(m_GPIO_KEY);
/*
if(mode == PinMode::ANALOG_MODE && getGPIOPortInfo(m_GPIO_KEY).ADCChannel == SHAL_ADC_Channel::NO_ADC_MAPPING){
char buff[100];
sprintf(buff, "Error: GPIO pin %d has no valid ADC mapping\r\n", static_cast<uint8_t>(m_GPIO_KEY));
SHAL_UART2.sendString(buff);
return SHAL_Result::ERROR;
}
*/
SHAL_set_bits(pinModeReg.reg,2,static_cast<uint8_t>(mode),pinModeReg.offset); //Set mode
return SHAL_Result::OKAY;
}
uint16_t SHAL_GPIO::digitalRead() const {
auto offset = getGPIOPinNumber(m_GPIO_KEY);
return (SHAL_check_bit(getGPIOInputDataRegister(m_GPIO_KEY).reg, 1 << offset)) ? 1 : 0;
}
/* TODO Fix implementation for STM32F072
void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {
uint32_t gpioPin = getGPIORegister(m_GPIO_KEY).global_offset; //Use existing structs to get offset
setPinMode(PinMode::INPUT_MODE); //Explicitly set mode to input
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; //Enable EXT, TODO check if this is different across STM32 models
NVIC_EnableIRQ(getGPIOEXTICR(m_GPIO_KEY).IRQN); //Enable IRQN for pin
EXTI->IMR |= (1 << gpioPin); //Enable correct EXTI line
SHAL_EXTIO_Register EXTILineEnable = getGPIOEXTICR(m_GPIO_KEY);
*EXTILineEnable.EXT_ICR |= EXTILineEnable.mask; //Set bits to enable correct port on correct line TODO Find way to clear bits before
uint32_t rising_mask = 0x00;
uint32_t falling_mask = 0x00;
//Set rising and falling edge triggers based on pin offset (enabled EXTI line)
switch(mode){
case TriggerMode::RISING_EDGE:
rising_mask = 1 << gpioPin;
break;
case TriggerMode::FALLING_EDGE:
falling_mask = 1 << gpioPin;
break;
case TriggerMode::RISING_FALLING_EDGE:
falling_mask = 1 << gpioPin;
falling_mask = 1 << gpioPin;
}
//Set triggers
EXTI->RTSR |= rising_mask;
EXTI->FTSR |= falling_mask;
//Set callback
registerEXTICallback(m_GPIO_KEY,callback);
__enable_irq(); //Enable IRQ just in case
}
*/
/* TODO reimplement
uint16_t SHAL_GPIO::analogRead(SHAL_ADC_SampleTime sampleTime) {
SHAL_ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
}
*/
SHAL_GPIO& GPIOManager::get(const uint8_t portNum, const uint8_t pinNum) {
uint8_t pinIndex = (PINS_PER_PORT * portNum) + pinNum;
initGPIO(static_cast<GPIO_Key>(pinIndex));
return m_gpios[portNum][pinNum];
}
void GPIOManager::initGPIO(GPIO_Key key) {
unsigned int gpioPort = getGPIOPortNumber(key);
uint8_t gpioPin = getGPIOPinNumber(key);
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
}
}
SHAL_GPIO& GPIOManager::get(const GPIO_Key key) {
initGPIO(key);
return m_gpios[getGPIOPortNumber(key)][getGPIOPinNumber(key)];
}

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SHAL/Src/STM32H7xx/Peripheral/Timer/SHAL_TIM.cpp Normal file
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//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM.h"
#include <cassert>
Timer::Timer(const Timer_Key t) : m_key(t){
}
Timer::Timer() : m_key(Timer_Key::S_TIM_INVALID){
}
void Timer::start() {
auto control_reg = getTimerControlRegister1(m_key);
auto event_reg = getTimerEventGenerationRegister(m_key);
auto status_reg = getTimerStatusRegister(m_key);
auto bdtr_reg = getTimerBreakDeadTimeRegister(m_key);
auto rcc_reg = getTimerRCC(m_key);
SHAL_apply_bitmask(event_reg.reg, event_reg.update_generation_mask);
SHAL_clear_bitmask(status_reg.reg, status_reg.update_interrupt_flag_mask);
SHAL_apply_bitmask(control_reg.reg, control_reg.auto_reload_preload_enable_mask);
SHAL_apply_bitmask(rcc_reg.reg, rcc_reg.enable_mask);
SHAL_apply_bitmask(control_reg.reg, control_reg.counter_enable_mask);
SHAL_apply_bitmask(bdtr_reg.reg, bdtr_reg.main_output_enable_mask);
enableInterrupt();
}
void Timer::stop() const {
auto control_reg = getTimerControlRegister1(m_key);
SHAL_clear_bitmask(control_reg.reg, control_reg.counter_enable_mask);
getTimerRegister(m_key)->CNT = 0;
// Force an update event to flush shadow registers NOW
auto event_reg = getTimerEventGenerationRegister(m_key);
SHAL_apply_bitmask(event_reg.reg, event_reg.update_generation_mask);
auto rcc_reg = getTimerRCC(m_key);
SHAL_clear_bitmask(rcc_reg.reg, rcc_reg.enable_mask);
}
void Timer::setPrescaler(const uint32_t presc) const {
auto prescalerReg = getTimerPrescalerRegister(m_key);
SHAL_set_register_value(prescalerReg.reg,presc);
}
void Timer::setARR(const uint32_t arr) const {
auto autoReloadReg = getTimerAutoReloadRegister(m_key);
SHAL_set_register_value(autoReloadReg.reg,arr);
}
void Timer::enableInterrupt() {
getTimerRegister(m_key)->DIER |= TIM_DIER_UIE;
NVIC_EnableIRQ(getIRQn(m_key));
}
void Timer::init(uint32_t prescaler, uint32_t autoReload) {
SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);
SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
setPrescaler(prescaler);
setARR(autoReload);
}
void Timer::init() const {
SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);
SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
}
void Timer::configurePWM(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {
setPrescaler(prescaler);
setARR(autoReload);
setCaptureCompareValue(channel, captureCompareThreshold);
setOutputCompareMode(channel, SHAL_TIM_Output_Compare_Mode::PWMMode1);
enableChannel(channel,SHAL_Timer_Channel_Main_Output_Mode::Polarity_Normal,SHAL_Timer_Channel_Complimentary_Output_Mode::Disabled);
}
void Timer::configureOneshot(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {
setPrescaler(prescaler);
setARR(autoReload);
setOutputCompareMode(channel, SHAL_TIM_Output_Compare_Mode::Toggle);
enableChannel(channel,SHAL_Timer_Channel_Main_Output_Mode::Polarity_Normal,SHAL_Timer_Channel_Complimentary_Output_Mode::Disabled);
setCaptureCompareValue(channel, captureCompareThreshold);
}
void Timer::setOutputCompareMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode) {
auto channelNum = static_cast<uint8_t>(channel);
auto CCMR = getTimerOutputCaptureCompareModeRegister(m_key, channel);
uint32_t OCMR_Offset = channelNum % 2 == 1 ? CCMR.output_compare_1_mode_offset : CCMR.output_compare_2_mode_offset;
SHAL_set_bits(CCMR.reg,3,static_cast<uint8_t>(outputCompareMode),OCMR_Offset);
}
void Timer::enableChannel(SHAL_Timer_Channel channel, SHAL_Timer_Channel_Main_Output_Mode mainOutputMode,
SHAL_Timer_Channel_Complimentary_Output_Mode complimentaryOutputMode) {
SHAL_TIM_Capture_Compare_Enable_Register captureCompareEnableReg = getTimerCaptureCompareEnableRegister(m_key, channel);
uint16_t setValue = 0; //Value to set the register as
auto channelNum = static_cast<uint8_t>(channel);
uint8_t channelStride = 4; //4 bits per field
setValue |= (static_cast<uint8_t>(mainOutputMode) << ((channelNum - 1) * channelStride)); //xxBB shifted by c - 1
setValue |= (static_cast<uint8_t>(complimentaryOutputMode) << (((channelNum - 1) * channelStride) + 2)); //BBxx shifted by c - 1
SHAL_set_register_value(captureCompareEnableReg.reg,setValue);
}
void Timer::setCaptureCompareValue(SHAL_Timer_Channel channel, uint32_t value) const {
auto captureCompareReg = getTimerCaptureCompareRegister(m_key,channel);
SHAL_set_register_value(captureCompareReg.reg,value);
}
Timer &TimerManager::get(Timer_Key timer_key) {
//Ensure that we don't try to get invalid timers
assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
Timer& selected = timers[static_cast<int>(timer_key)];
//Timer queried is not initialized yet (defaults to invalid)
if(selected.m_key == Timer_Key::S_TIM_INVALID){
timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
}
return timers[static_cast<int>(timer_key)];
}

0
SHAL/Src/STM32L4XX/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp → SHAL/Src/STM32H7xx/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp
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87
SHAL/Src/STM32H7xx/Peripheral/UART/SHAL_UART.cpp Normal file
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/**
******************************************************************************
* @file SHAL_TIM.h
* @author Luca Lizaranzu
* @brief Related to USART and SHAL_UART abstractions
******************************************************************************
*/
#include "SHAL_UART.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART_REG.h"
void SHAL_UART::init(const UART_Pair_Key pair){
m_key = pair;
auto uartPair = getUARTPair(pair); //Get the UART_PAIR information to be initialized
//Get the SHAL_GPIO pins for this SHAL_UART setup
const GPIO_Key Tx_Key = uartPair.TxKey; //Tx pin
const GPIO_Key Rx_Key = uartPair.RxKey; //Rx pin
GET_GPIO(Tx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
GET_GPIO(Rx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
GET_GPIO(Tx_Key).setAlternateFunction(uartPair.TxAlternateFunctionMask);
GET_GPIO(Rx_Key).setAlternateFunction(uartPair.RxAlternateFunctionMask);
SHAL_UART_Enable_Register pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the SHAL_UART channel
SHAL_apply_bitmask(pairUARTEnable.reg,pairUARTEnable.mask);
}
void SHAL_UART::begin(uint32_t baudRate, SHAL_USART_Word_Length wordLength) const volatile {
auto CR = getUARTControlRegister1(m_key);
auto BRR = getUARTBaudRateRegister(m_key); // fix this
SHAL_clear_bitmask(CR.reg, CR.usart_enable_mask);
SHAL_apply_bitmask(CR.reg, static_cast<uint32_t>(wordLength));
SHAL_apply_bitmask(CR.reg, CR.receive_enable_mask);
SHAL_apply_bitmask(CR.reg, CR.transmit_enable_mask);
SHAL_apply_bitmask(CR.reg, CR.Rx_interrupt_enable_mask);
SHAL_set_register_value(getUARTTransmitDataRegister(m_key).reg,0); //Clear TDR
uint16_t baud = SystemCoreClock / (1 * baudRate);
SHAL_set_bits_16(BRR.reg, 16, baud, 0);
SHAL_apply_bitmask(CR.reg, CR.usart_enable_mask); //Enable
}
void SHAL_UART::sendString(const char *s) const volatile {
const auto ISR = getUARTISR(m_key);
while (*s) sendChar(*s++); //Send chars while we haven't reached end of s
if (!SHAL_wait_for_bit_set_us(ISR.reg, ISR.transmit_data_register_empty_mask, 500)) {
assert(false);
}
}
void SHAL_UART::sendChar(const char c) const volatile {
const auto ISR = getUARTISR(m_key);
SHAL_wait_for_bit_set_us(ISR.reg,ISR.transmit_data_register_empty_mask,500);
SHAL_set_register_value(getUARTTransmitDataRegister(m_key).reg,static_cast<uint32_t>(c));
}
SHAL_UART& UARTManager::get(uint8_t uart) {
if(uart > NUM_USART_LINES - 1){
assert(false);
//Memory fault
}
return m_UARTs[uart];
}

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SHAL/Src/STM32H7xx/System/system_stm32h7xx.c Normal file
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/**
******************************************************************************
* @file system_stm32h7xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - ExitRun0Mode(): Specifies the Power Supply source. This function is
* called at startup just after reset and before the call
* of SystemInit(). This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/** @addtogroup STM32H7xx_System_Private_Includes
* @{
*/
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
/* #define DATA_IN_D2_SRAM */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
#if defined(DUAL_CORE) && defined(CORE_CM4)
/*!< Uncomment the following line if you need to relocate your vector Table
in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#else
/*!< Uncomment the following line if you need to relocate your vector Table
in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#endif /* DUAL_CORE && CORE_CM4 */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting and vector table location
* configuration.
* @param None
* @retval None
*/
void SystemInit (void)
{
#if defined (DATA_IN_D2_SRAM)
__IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
#if defined(D3_SRAM_BASE)
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
#else
/* Reset CDCFGR1 register */
RCC->CDCFGR1 = 0x00000000;
/* Reset CDCFGR2 register */
RCC->CDCFGR2 = 0x00000000;
/* Reset SRDCFGR register */
RCC->SRDCFGR = 0x00000000;
#endif
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x02020200;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x01FF0000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x01010280;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x01010280;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x01010280;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */
RCC->CIER = 0x00000000;
#if (STM32H7_DEV_ID == 0x450UL)
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif /* STM32H7_DEV_ID */
#if defined(DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM3EN */
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
#endif /* DATA_IN_D2_SRAM */
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#else
if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
{
/* Enable the FMC interface clock */
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
/* Disable the FMC interface clock */
CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
}
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /*DUAL_CORE && CORE_CM4*/
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
common_system_clock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
common_system_clock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
if (pllm != 0U)
{
switch (pllsource)
{
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
default:
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
common_system_clock = 0U;
}
break;
default:
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
#if defined (RCC_D1CFGR_D1CPRE)
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
}
/**
* @brief Exit Run* mode and Configure the system Power Supply
*
* @note This function exits the Run* mode and configures the system power supply
* according to the definition to be used at compilation preprocessing level.
* The application shall set one of the following configuration option:
* - PWR_LDO_SUPPLY
* - PWR_DIRECT_SMPS_SUPPLY
* - PWR_EXTERNAL_SOURCE_SUPPLY
* - PWR_SMPS_1V8_SUPPLIES_LDO
* - PWR_SMPS_2V5_SUPPLIES_LDO
* - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
* - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
* - PWR_SMPS_1V8_SUPPLIES_EXT
* - PWR_SMPS_2V5_SUPPLIES_EXT
*
* @note The function modifies the PWR->CR3 register to enable or disable specific
* power supply modes and waits until the voltage level flag is set, indicating
* that the power supply configuration is stable.
*
* @param None
* @retval None
*/
void ExitRun0Mode(void)
{
#if defined(USE_PWR_LDO_SUPPLY)
#if defined(SMPS)
/* Exit Run* mode by disabling SMPS and enabling LDO */
PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN;
#else
/* Enable LDO mode */
PWR->CR3 |= PWR_CR3_LDOEN;
#endif /* SMPS */
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY)
#if defined(SMPS)
/* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
#else
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
#endif /* SMPS */
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
/* Exit Run* mode */
PWR->CR3 &= ~(PWR_CR3_LDOEN);
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
/* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
/* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
/* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
/* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
/* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
/* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#else
/* No system power supply configuration is selected at exit Run* mode */
#endif /* USE_PWR_LDO_SUPPLY */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

158
SHAL/Src/STM32L4XX/Peripheral/ADC/SHAL_ADC.cpp
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@@ -1,158 +0,0 @@
//
// Created by Luca on 9/21/2025.
//
#include "SHAL_ADC.h"
//Can hard code registers on F0 because all F0 devices have only one ADC, and use only one clock
SHAL_Result SHAL_ADC::init() {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return SHAL_Result::ERROR;
}
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
SHAL_ADC_RCC_Enable_Reg clock_reg = getADCRCCEnableRegister(m_ADCKey); //Clock enable
*clock_reg.reg |= clock_reg.mask;
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
if (*control_reg.reg & control_reg.enable_mask) {
//request disable: ADEN=1 -> set ADDIS to disable
*control_reg.reg |= control_reg.disable_mask;
//wait until ADEN cleared (ISR.ADREADY == 0)
if(!SHAL_WAIT_FOR_CONDITION_MS((*control_reg.reg & control_reg.enable_mask) == 0, 100)){
return SHAL_Result::ERROR;
}
}
if(calibrate() != SHAL_Result::OKAY){ //Calibrate
return SHAL_Result::ERROR;
}
configureAlignment(SHAL_ADC_Alignment::RIGHT);
configureResolution(SHAL_ADC_Resolution::B12);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::calibrate() {
if(disable() != SHAL_Result::OKAY){ //Disable the ADC
return SHAL_Result::ERROR;
}
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
*control_reg.reg |= control_reg.calibration_mask;
if(!SHAL_WAIT_FOR_CONDITION_US(((*control_reg.reg & control_reg.calibration_mask) == 0),500)){ //Wait for calibration
return SHAL_Result::ERROR;
}
return SHAL_Result::OKAY;
}
uint16_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_TSEN; //Enable VREFINT and Temp sensor in global ADC struct
ADC_reg->CHSELR = static_cast<uint32_t>(channel); //Enable channel for conversion
ADC_reg->SMPR |= static_cast<uint32_t>(time); //Set sampling time
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_EOC) != 0),500)){ //Wait for conversion
return 0; //Failed
}
uint16_t result = ADC_reg->DR;
return result;
}
void SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, const int numChannels, uint16_t* result, ADC_SampleTime time) {
ADC_TypeDef* ADC_reg = getADCRegister(m_ADCKey);
ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_TSEN; //Enable VREFINT and Temp sensor in global ADC struct
for(int i = 0; i < numChannels; i++){ //Enable all channels
ADC_reg->CHSELR = static_cast<uint32_t>(channels[i]);
}
ADC_reg->SMPR |= static_cast<uint32_t>(time); //Set sampling time
for(int i = 0; i < numChannels; i++){
if(!SHAL_WAIT_FOR_CONDITION_US(((ADC_reg->ISR & ADC_ISR_EOC) != 0),500)){ //Wait for conversion
continue; //Failed
}
result[i] = ADC_reg->DR;
}
}
SHAL_Result SHAL_ADC::disable() {
if(!isValid()){
return SHAL_Result::ERROR;
}
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
if (*control_reg.reg & control_reg.enable_mask) {
//request disable: ADEN=1 -> set ADDIS to disable
*control_reg.reg |= control_reg.disable_mask;
//wait until ADEN cleared (ISR.ADREADY == 0)
if(!SHAL_WAIT_FOR_CONDITION_MS((*control_reg.reg & control_reg.enable_mask) == 0, 100)){
return SHAL_Result::ERROR;
}
}
return SHAL_Result::OKAY;
}
bool SHAL_ADC::isValid() {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return false;
}
return true;
}
SHAL_Result SHAL_ADC::configureResolution(SHAL_ADC_Resolution resolution) {
if(!isValid()){
return SHAL_Result::ERROR;
}
SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
SHAL_set_bits(config_reg.reg,2,static_cast<uint8_t>(resolution),config_reg.resolution_offset);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::configureAlignment(SHAL_ADC_Alignment alignment) {
if(!isValid()){
return SHAL_Result::ERROR;
}
SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
*config_reg.reg &= ~(0x1UL << config_reg.alignment_offset); //TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
*config_reg.reg |= static_cast<uint8_t>(alignment) << config_reg.alignment_offset;
return SHAL_Result::OKAY;
}
SHAL_ADC &ADCManager::get(ADC_Key key) {
return m_ADCs[static_cast<uint8_t>(key)];
}
SHAL_ADC& ADCManager::getByIndex(int index) {
if(index < static_cast<int>(ADC_Key::NUM_ADC)){
return m_ADCs[index];
}
return m_ADCs[0];
}

128
SHAL/Src/STM32L4XX/Peripheral/GPIO/SHAL_GPIO.cpp
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@@ -1,128 +0,0 @@
//
// Created by Luca on 8/30/2025.
//
#include "SHAL_GPIO.h"
#include "SHAL_EXTI_CALLBACK.h"
SHAL_GPIO::SHAL_GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
volatile unsigned long* gpioEnable = getGPIORCCEnable(key).reg;
unsigned long gpioOffset = getGPIORCCEnable(key).offset;
*gpioEnable |= (1 << gpioOffset); //Set enable flag
}
void SHAL_GPIO::setLow() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR &= ~(1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setHigh() {
auto gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR |= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::toggle() volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->ODR ^= (1 << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setPinType(PinType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OTYPER &= ~(1 << gpioPeripheral.global_offset);
gpioPeripheral.reg->OTYPER |= (static_cast<uint8_t>(type) << gpioPeripheral.global_offset);
}
void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->OSPEEDR |= (static_cast<uint8_t>(speed) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setInternalResistor(InternalResistorType type) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->PUPDR &= ~(0x03 << (2 * gpioPeripheral.global_offset));
gpioPeripheral.reg->PUPDR |= (static_cast<uint8_t>(type) << (2 * gpioPeripheral.global_offset));
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
int afrIndex = gpioPeripheral.global_offset < 8 ? 0 : 1; //Get index of AFR
gpioPeripheral.reg->AFR[afrIndex] &= ~(0xF << (gpioPeripheral.global_offset * 4));
gpioPeripheral.reg->AFR[afrIndex] |= (static_cast<int>(AF) << (gpioPeripheral.global_offset * 4));
}
void SHAL_GPIO::setPinMode(PinMode mode) volatile {
SHAL_GPIO_Peripheral gpioPeripheral = getGPIORegister(m_GPIO_KEY);
gpioPeripheral.reg->MODER &= ~(0x03 << (2 * gpioPeripheral.global_offset)); //Clear any previous mode
gpioPeripheral.reg->MODER |= (static_cast<uint8_t>(mode) << (2 * gpioPeripheral.global_offset)); //Set mode based on pinmode bit structure
}
void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {
uint32_t gpioPin = getGPIORegister(m_GPIO_KEY).global_offset; //Use existing structs to get offset
setPinMode(PinMode::INPUT_MODE); //Explicitly set mode to input
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; //Enable EXT, TODO check if this is different across STM32 models
NVIC_EnableIRQ(getGPIOEXTICR(m_GPIO_KEY).IRQN); //Enable IRQN for pin
EXTI->IMR |= (1 << gpioPin); //Enable correct EXTI line
SHAL_EXTIO_Register EXTILineEnable = getGPIOEXTICR(m_GPIO_KEY);
*EXTILineEnable.EXT_ICR |= EXTILineEnable.mask; //Set bits to enable correct port on correct line TODO Find way to clear bits before
uint32_t rising_mask = 0x00;
uint32_t falling_mask = 0x00;
//Set rising and falling edge triggers based on pin offset (enabled EXTI line)
switch(mode){
case TriggerMode::RISING_EDGE:
rising_mask = 1 << gpioPin;
break;
case TriggerMode::FALLING_EDGE:
falling_mask = 1 << gpioPin;
break;
case TriggerMode::RISING_FALLING_EDGE:
falling_mask = 1 << gpioPin;
falling_mask = 1 << gpioPin;
}
//Set triggers
EXTI->RTSR |= rising_mask;
EXTI->FTSR |= falling_mask;
//Set callback
registerEXTICallback(m_GPIO_KEY,callback);
__enable_irq(); //Enable IRQ just in case
}
uint16_t SHAL_GPIO::analogRead(ADC_SampleTime sampleTime) {
SHAL_ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
}
SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
unsigned int gpioPort = getGPIOPortNumber(key);
unsigned long gpioPin = getGPIORegister(key).global_offset; //Use existing structs to get offset
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
}
return m_gpios[gpioPort][gpioPin];
}

63
SHAL/Src/STM32L4XX/Peripheral/Timer/SHAL_TIM.cpp
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@@ -1,63 +0,0 @@
//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM.h"
#include <cassert>
Timer::Timer(Timer_Key t) : TIMER_KEY(t){
}
Timer::Timer() : TIMER_KEY(Timer_Key::S_TIM_INVALID){
}
void Timer::start() {
getTimerRegister(TIMER_KEY)->CR1 |= TIM_CR1_CEN;
getTimerRegister(TIMER_KEY)->EGR |= TIM_EGR_UG; //load prescaler reg and ARR
enableInterrupt();
}
void Timer::stop() {
getTimerRegister(TIMER_KEY)->CR1 &= ~TIM_CR1_CEN;
}
void Timer::setPrescaler(uint16_t presc) {
getTimerRegister(TIMER_KEY)->PSC = presc;
}
void Timer::setARR(uint16_t arr) {
getTimerRegister(TIMER_KEY)->ARR = arr;
}
void Timer::enableInterrupt() {
getTimerRegister(TIMER_KEY)->DIER |= TIM_DIER_UIE;
NVIC_EnableIRQ(getIRQn(TIMER_KEY));
}
void Timer::init(uint32_t prescaler, uint32_t autoReload) {
TIM_RCC_Enable rcc = getTimerRCC(TIMER_KEY);
*rcc.busEnableReg |= (1 << rcc.offset);
setPrescaler(prescaler);
setARR(autoReload);
}
Timer &TimerManager::get(Timer_Key timer_key) {
//Ensure that we don't try to get invalid timers
assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
Timer& selected = timers[static_cast<int>(timer_key)];
//Timer queried is not initialized yet (defaults to invalid)
if(selected.TIMER_KEY == Timer_Key::S_TIM_INVALID){
timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
}
return timers[static_cast<int>(timer_key)];
}

23
SHAL/Src/STM32L4XX/Core/SHAL_CORE.cpp → SHAL/Src/STM32L4xx/Core/SHAL_CORE.cpp
View File

@@ -2,10 +2,25 @@
// Created by Luca on 9/15/2025.
//
#include <cstdio>
#include "SHAL_CORE.h"
#include "SHAL_GPIO.h"
#include "SHAL_ADC.h"
#include "SHAL_UART.h"
void SHAL_init(){
systick_init(); //Just this for now
systick_init();
for(auto i = static_cast<uint8_t>(ADC_Key::S_ADC1); i < static_cast<uint8_t>(ADC_Key::NUM_ADC); i++){ //Init all ADCs
auto adc_key = static_cast<ADC_Key>(i);
ADCManager::getByIndex(i).init(adc_key);
}
SET_ANALOGREAD_ADC(SHAL_ADC1); //Default ADC1 for analogread calls
}
@@ -40,3 +55,9 @@ void SHAL_delay_ms(uint32_t ms){
SHAL_delay_us(1000);
}
}
void SHAL_print_register(const volatile uint32_t* reg){
char buff[32];
sprintf(buff, "0x%08lX\r\n", (unsigned long)(*reg));
SHAL_UART2.sendString(buff);
}

10
SHAL/Src/STM32L4XX/EXT/SHAL_EXTI_CALLBACK.cpp → SHAL/Src/STM32L4xx/EXT/SHAL_EXTI_CALLBACK.cpp
View File

@@ -9,7 +9,13 @@
#elif defined(STM32L422xx)
#elif defined(STM32L431xx)
#elif defined(STM32L432xx)
DEFINE_EXTI_IRQ()
DEFINE_EXTI_IRQ(0);
DEFINE_EXTI_IRQ(1);
DEFINE_EXTI_IRQ(2);
DEFINE_EXTI_IRQ(3);
DEFINE_EXTI_IRQ(4);
DEFINE_MULTI_EXTI_IRQ(5,9);
DEFINE_MULTI_EXTI_IRQ(10,15);
#elif defined(STM32L433xx)
#elif defined(STM32L442xx)
#elif defined(STM32L443xx)
@@ -37,5 +43,5 @@ DEFINE_EXTI_IRQ()
//Link function to EXTI line
void registerEXTICallback(GPIO_Key key, EXTICallback callback){
EXTI_callbacks[getGPIORegister(key).global_offset] = callback;
EXTI_callbacks[getGPIOPinNumber(key)] = callback;
}

308
SHAL/Src/STM32L4xx/Peripheral/ADC/SHAL_ADC.cpp Normal file
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@@ -0,0 +1,308 @@
//
// Created by Luca on 9/21/2025.
//
#include "SHAL_ADC.h"
#include "SHAL_GPIO.h"
#include "SHAL_UART.h"
#include <cstdio>
SHAL_Result SHAL_ADC::init(ADC_Key key) {
m_ADCKey = key;
if(!isValid()){
SHAL_UART2.sendString("Not valid\r\n");
return SHAL_Result::ERROR;
}
SHAL_ADC_RCC_Enable_Reg clock_reg = getADCRCCEnableRegister(m_ADCKey); //Clock enable
SHAL_apply_bitmask(clock_reg.reg,clock_reg.mask);
auto clock_select_register = getADCClockSelectRegister();
SHAL_set_bits(clock_select_register.reg, 2, static_cast<uint32_t>(ADC_Clock_Source::SHAL_SYSCLK),clock_select_register.offset); //Set ADC clock
wakeFromDeepSleep();
if(calibrate() != SHAL_Result::OKAY){ //Calibrate
SHAL_UART2.sendString("Calibration failed");
return SHAL_Result::ERROR;
}
if(enable() != SHAL_Result::OKAY){
SHAL_UART2.sendString("Could not enable from init\r\n");
return SHAL_Result::ERROR;
}
configureAlignment(SHAL_ADC_Alignment::RIGHT);
configureResolution(SHAL_ADC_Resolution::B12);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::calibrate() {
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
if(disable() != SHAL_Result::OKAY){
return SHAL_Result::ERROR;
}
SHAL_delay_us(1000);
if ((*control_reg.reg & (control_reg.enable_mask | control_reg.disable_mask)) != 0) {
return SHAL_Result::ERROR;
}
SHAL_clear_bitmask(control_reg.reg, control_reg.differential_mode_mask);
SHAL_apply_bitmask(control_reg.reg, control_reg.calibration_mask);
if ((*control_reg.reg & control_reg.calibration_mask) == 0) {
return SHAL_Result::ERROR;
}
if (!SHAL_WAIT_FOR_CONDITION_US(((*control_reg.reg & control_reg.calibration_mask) != 0),500)) { //Wait for conversion
return SHAL_Result::ERROR; //Failed sequence
}
SHAL_UART2.sendString("Calibration OK\r\n");
return SHAL_Result::OKAY;
}
uint16_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time) {
auto data_reg = getADCDataReg(m_ADCKey);
auto ISR_reg = getADCISRReg(m_ADCKey);
auto config_reg = getADCConfigReg(m_ADCKey);
SHAL_clear_bitmask(config_reg.reg, config_reg.continuous_mode_mask);
auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey, channel);
SHAL_set_bits(sampleTimeReg.reg, 3, static_cast<uint8_t>(time), sampleTimeReg.channel_offset);
addADCChannelToSequence(channel, 0);
if(setADCSequenceAmount(1) == SHAL_Result::ERROR) { return 0; }
if(enable() != SHAL_Result::OKAY) {
return 0;
}
// CRITICAL: Clear ALL relevant flags before starting
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.end_of_sequence_mask);
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.end_of_conversion_mask);
if(ISR_reg.overrun_mask) {
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.overrun_mask);
}
volatile uint16_t dummy = *data_reg.reg;
(void)dummy;
startConversion();
if(!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_conversion_mask) != 0), 2000)) {
return 0;
}
uint16_t result = *data_reg.reg;
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.end_of_conversion_mask);
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.end_of_sequence_mask);
return result;
}
SHAL_Result SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time) {
auto data_reg = getADCDataReg(m_ADCKey); //Where our output will be stored
setADCSequenceAmount(numChannels); //Convert the correct amount of channels
for(int i = 0; i < numChannels; i++){
auto channel = channels[i];
auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey,channel);
SHAL_set_bits(sampleTimeReg.reg,3,static_cast<uint8_t>(time),sampleTimeReg.channel_offset); //Set sample time register TODO un-hardcode bit width?
addADCChannelToSequence(channel,i); //Use index 0 to convert channel
}
startConversion(); //Start ADC conversion
auto ISR_reg = getADCISRReg(m_ADCKey);
for(int i = 0; i < numChannels; i++) {
if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_conversion_mask) != 0),500)) { //Wait for conversion
return SHAL_Result::ERROR; //Failed conversion
}
result[i] = *data_reg.reg;
}
if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_sequence_mask) != 0),500)) { //Wait for conversion
return SHAL_Result::ERROR; //Failed sequence
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::enable() {
if(!isValid()){
SHAL_UART2.sendString("Enable failed: Invalid \r\n");
return SHAL_Result::ERROR;
}
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
if(!SHAL_WAIT_FOR_CONDITION_MS((*control_reg.reg & control_reg.calibration_mask) == 0, 100)) {
return SHAL_Result::ERROR;
}
if (*control_reg.reg & control_reg.enable_mask) {
return SHAL_Result::OKAY; //Not an error
}
if (*control_reg.reg & control_reg.disable_mask) {
return SHAL_Result::ERROR;
}
//Clear ADRDY flag by writing 1 to it
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask);
//Enable the ADC by setting ADEN
SHAL_apply_bitmask(control_reg.reg, control_reg.enable_mask);
if(!SHAL_WAIT_FOR_CONDITION_MS((*ISR_reg.reg & ISR_reg.ready_mask) != 0, 100)) {
return SHAL_Result::ERROR;
}
//Clear ADRDY again
SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::wakeFromDeepSleep() {
SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey); //ADC Control register
SHAL_clear_bitmask(control_reg.reg,control_reg.deep_power_down_mask); //Wake ADC from sleep
SHAL_apply_bitmask(control_reg.reg,control_reg.voltage_regulator_mask);
SHAL_delay_us(50); //Wait for regulator to stabilize
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::disable() {
if(!isValid()){
return SHAL_Result::ERROR;
}
auto control_reg = getADCControlReg(m_ADCKey);
//Stop any ongoing conversion
if (*control_reg.reg & control_reg.start_mask) {
SHAL_apply_bitmask(control_reg.reg, control_reg.stop_mask);
}
//Only disable if ADC is enabled otherwise it hangs
if (*control_reg.reg & control_reg.enable_mask) {
SHAL_apply_bitmask(control_reg.reg, control_reg.disable_mask);
if (!SHAL_WAIT_FOR_CONDITION_MS(((*control_reg.reg & (control_reg.enable_mask | control_reg.disable_mask)) == 0),500)){
return SHAL_Result::ERROR;
}
}
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::startConversion() {
auto control_reg = getADCControlReg(m_ADCKey);
SHAL_apply_bitmask(control_reg.reg,control_reg.start_mask);
return SHAL_Result::OKAY;
}
bool SHAL_ADC::isValid() {
if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
return false;
}
return true;
}
SHAL_Result SHAL_ADC::configureResolution(SHAL_ADC_Resolution resolution) {
if(!isValid()){
return SHAL_Result::ERROR;
}
SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
SHAL_set_bits(config_reg.reg,2,static_cast<uint8_t>(resolution),config_reg.resolution_offset);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::configureAlignment(SHAL_ADC_Alignment alignment) {
if(!isValid()){
return SHAL_Result::ERROR;
}
SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
//TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
SHAL_set_bits(config_reg.reg,1,static_cast<uint8_t>(alignment),config_reg.alignment_offset);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::setADCSequenceAmount(uint32_t amount) {
if(!isValid()){return SHAL_Result::ERROR;}
if(amount == 0){
return SHAL_Result::ERROR;
}
SHAL_ADC_Sequence_Amount_Reg sequence_amount_reg = getADCSequenceAmountRegister(m_ADCKey);
SHAL_set_bits(sequence_amount_reg.reg, 4, amount - 1, sequence_amount_reg.offset);
return SHAL_Result::OKAY;
}
SHAL_Result SHAL_ADC::addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t index) {
if(!isValid()) { return SHAL_Result::ERROR; }
auto sequenceRegisters = getADCSequenceRegisters(m_ADCKey);
auto channelNum = static_cast<uint8_t>(channel);
uint32_t bitSection = (index + 1) % 5;
uint32_t sequenceRegNumber = (index + 1) / 5;
volatile uint32_t* sequenceReg = sequenceRegisters.regs[sequenceRegNumber];
uint32_t bitSectionOffset = sequenceRegisters.offsets[bitSection];
// Clear only the specific 5 bits we're setting, not the entire register
uint32_t clearMask = ~(0x1F << bitSectionOffset);
*sequenceReg &= clearMask;
// Set the new channel number
*sequenceReg |= (channelNum << bitSectionOffset);
return SHAL_Result::OKAY;
}
SHAL_ADC &ADCManager::get(ADC_Key key) {
return m_ADCs[static_cast<uint8_t>(key)];
}
SHAL_ADC& ADCManager::getByIndex(int index) {
if(index < static_cast<int>(ADC_Key::NUM_ADC)){
return m_ADCs[index];
}
return m_ADCs[0];
}

126
SHAL/Src/STM32L4xx/Peripheral/GPIO/SHAL_GPIO.cpp Normal file
View File

@@ -0,0 +1,126 @@
//
// Created by Luca on 8/30/2025.
//
#include <cstdio>
#include "SHAL_GPIO.h"
#include "SHAL_EXTI_CALLBACK.h"
#include "SHAL_UART.h"
SHAL_GPIO::SHAL_GPIO() : m_GPIO_KEY(GPIO_Key::INVALID){
//Do not initialize anything
}
SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
volatile unsigned long* gpioEnable = getGPIORCCEnable(key).reg;
unsigned long gpioOffset = getGPIORCCEnable(key).offset;
*gpioEnable |= (1 << gpioOffset); //Set enable flag
}
void SHAL_GPIO::setLow() {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_set_bits(outputDataReg.reg,1,0,outputDataReg.offset);
}
void SHAL_GPIO::setHigh() {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_set_bits(outputDataReg.reg,1,1,outputDataReg.offset);
}
void SHAL_GPIO::toggle() volatile {
auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
SHAL_flip_bits(outputDataReg.reg,1,outputDataReg.offset);
}
void SHAL_GPIO::setOutputType(PinType type) volatile {
auto outputTypeReg = getGPIOOutputTypeRegister(m_GPIO_KEY);
SHAL_set_bits(outputTypeReg.reg,2,static_cast<uint8_t>(type),outputTypeReg.offset);
}
void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) volatile {
auto outputSpeedReg = getGPIOOutputSpeedRegister(m_GPIO_KEY);
SHAL_set_bits(outputSpeedReg.reg,2,static_cast<uint8_t>(speed),outputSpeedReg.offset);
}
void SHAL_GPIO::setInternalResistor(InternalResistorType type) volatile {
auto pupdreg = getGPIOPUPDRegister(m_GPIO_KEY);
SHAL_set_bits(pupdreg.reg,2,static_cast<uint8_t>(type),pupdreg.offset);
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) volatile {
auto alternateFunctionReg = getGPIOAlternateFunctionRegister(m_GPIO_KEY);
SHAL_set_bits(alternateFunctionReg.reg,4,static_cast<uint8_t>(AF),alternateFunctionReg.offset);
}
SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) volatile {
auto pinModeReg = getGPIOModeRegister(m_GPIO_KEY);
if(mode == PinMode::ANALOG_MODE && getGPIOPortInfo(m_GPIO_KEY).ADCChannel == SHAL_ADC_Channel::NO_ADC_MAPPING){
char buff[100];
sprintf(buff, "Error: GPIO pin %d has no valid ADC mapping\r\n", static_cast<uint8_t>(m_GPIO_KEY));
SHAL_UART2.sendString(buff);
return SHAL_Result::ERROR;
}
SHAL_set_bits(pinModeReg.reg,2,static_cast<uint8_t>(mode),pinModeReg.offset); //Set mode
return SHAL_Result::OKAY;
}
void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {
/* ---- Connect PB6 to EXTI6 via SYSCFG ---- */
uint32_t port_b_val = 1; // 0=A, 1=B, 2=C, 3=D, etc.
SYSCFG->EXTICR[1] &= ~(0xFUL << 8); // Clear EXTI6 bits (bits 8-11)
SYSCFG->EXTICR[1] |= (port_b_val << 8); // Set EXTI6 to PB6
/* ---- Configure EXTI line 6 ---- */
EXTI->IMR1 |= (1UL << 6); // Unmask line 6
EXTI->RTSR1 |= (1UL << 6); // Rising trigger enable
EXTI->FTSR1 &= ~(1UL << 6); // Falling trigger disable
/* ---- Enable NVIC interrupt for EXTI lines [9:5] ---- */
NVIC_SetPriority(EXTI9_5_IRQn, 2);
NVIC_EnableIRQ(EXTI9_5_IRQn);
__enable_irq(); //Enable IRQ just in case
}
uint16_t SHAL_GPIO::analogRead(SHAL_ADC_SampleTime sampleTime) {
SHAL_ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;
return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
}
void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function_Mapping AF) volatile {
setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
auto alternateFunctionReg = getGPIOAlternateFunctionRegister(m_GPIO_KEY);
SHAL_set_bits(alternateFunctionReg.reg,4,static_cast<uint8_t>(AF),alternateFunctionReg.offset);
}
uint16_t SHAL_GPIO::digitalRead() {
auto inputDataReg = getGPIOInputDataRegister(m_GPIO_KEY);
if((*inputDataReg.reg & (1 << 6)) != 0){
return 1;
}
return 0;
}
SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
unsigned int gpioPort = getGPIOPortNumber(key);
uint8_t gpioPin = getGPIOPinNumber(key);
if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
}
return m_gpios[gpioPort][gpioPin];
}

5
SHAL/Src/STM32F0XX/Peripheral/I2C/SHAL_I2C.cpp → SHAL/Src/STM32L4xx/Peripheral/I2C/SHAL_I2C.cpp
View File

@@ -27,8 +27,8 @@ void SHAL_I2C::init(I2C_Pair pair) volatile {
GET_GPIO(SDA_Key).setAlternateFunction(I2CPair.SDA_Mask);
//These may be abstracted further to support multiple I2C configurations
GET_GPIO(SCL_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SDA_Key).setPinType(PinType::OPEN_DRAIN);
GET_GPIO(SCL_Key).setOutputType(PinType::OPEN_DRAIN);
GET_GPIO(SDA_Key).setOutputType(PinType::OPEN_DRAIN);
GET_GPIO(SCL_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
GET_GPIO(SDA_Key).setOutputSpeed(OutputSpeed::HIGH_SPEED);
@@ -79,7 +79,6 @@ void SHAL_I2C::masterWriteRead(uint8_t addr,const uint8_t* writeData, size_t wri
for (size_t i = 0; i < writeLen; i++) {
if(!SHAL_WAIT_FOR_CONDITION_MS((I2CPeripheral->ISR & I2C_ISR_TXIS) != 0, 100)){
SHAL_UART2.sendString("I2C timed out waiting for TX\r\n");
return;
}
I2CPeripheral->TXDR = writeData[i];

117
SHAL/Src/STM32L4xx/Peripheral/Timer/SHAL_TIM.cpp Normal file
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@@ -0,0 +1,117 @@
//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM.h"
#include <cassert>
Timer::Timer(Timer_Key key) : m_key(key){
}
Timer::Timer() : m_key(Timer_Key::S_TIM_INVALID){
}
void Timer::start() {
auto control_reg = getTimerControlRegister1(m_key);
auto event_generation_reg = getTimerEventGenerationRegister(m_key);
auto status_reg = getTimerStatusRegister(m_key);
SHAL_apply_bitmask(control_reg.reg, control_reg.counter_enable_mask); //Enable counter
SHAL_apply_bitmask(control_reg.reg, control_reg.auto_reload_preload_enable_mask); //Preload enable (buffer)
SHAL_apply_bitmask(event_generation_reg.reg, event_generation_reg.update_generation_mask);
SHAL_clear_bitmask(status_reg.reg,status_reg.update_interrupt_flag_mask);
enableInterrupt();
}
void Timer::stop() {
auto control_reg = getTimerControlRegister1(m_key);
SHAL_clear_bitmask(control_reg.reg, control_reg.counter_enable_mask); //Enable counter
}
void Timer::setPrescaler(uint16_t presc) {
auto prescaler_reg = getTimerPrescalerRegister(m_key);
SHAL_set_register_value(prescaler_reg.reg,presc);
}
void Timer::setARR(uint16_t arr) {
auto autoreload_reg = getTimerAutoReloadRegister(m_key);
SHAL_set_register_value(autoreload_reg.reg,arr);
}
void Timer::enableInterrupt() {
auto dma_ier = getTimerDMAInterruptEnableRegister(m_key);
SHAL_apply_bitmask(dma_ier.reg,dma_ier.update_interrupt_enable_mask);
NVIC_EnableIRQ(getTimerIRQn(m_key)); //Enable the IRQn in the NVIC
}
void Timer::init(uint16_t prescaler, uint16_t autoReload) {
SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);
SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
setPrescaler(prescaler);
setARR(autoReload);
*getTimerStatusRegister(m_key).reg = 0;
*getTimerDMAInterruptEnableRegister(m_key).reg = 0;
}
void Timer::setPWMMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode, SHAL_Timer_Channel_Main_Output_Mode mainOutputMode,
SHAL_Timer_Channel_Complimentary_Output_Mode complimentaryOutputMode) {
auto ccer = getTimerCaptureCompareEnableRegister(m_key);
auto ccmr1 = getTimerCaptureCompareModeRegistersOutput(m_key);
auto bdtr = getTimerBreakDeadTimeRegister(m_key);
uint8_t fullChannelModeMask = static_cast<uint8_t>(mainOutputMode) | (static_cast<uint8_t>(complimentaryOutputMode) << 2);
uint8_t channelNum = static_cast<uint8_t>(channel);
if (channelNum <= 3) {
uint32_t regNum = channelNum / 2; //TODO change later for support for channels 5 and 6
if (channelNum % 2 == 1) {
SHAL_set_bits(ccmr1.regs[regNum], 4, static_cast<uint8_t>(outputCompareMode),
ccmr1.output_compare_2_mode_offset);
} else {
SHAL_set_bits(ccmr1.regs[regNum], 4, static_cast<uint8_t>(outputCompareMode),
ccmr1.output_compare_1_mode_offset);
}
}
uint32_t offset = channelNum * 4;
if (static_cast<uint8_t>(m_key) > 3) {
fullChannelModeMask &= (0b0011); //Clear bits for complimentary output since channels 4,5,6 don't support it
}
SHAL_set_bits(ccer.reg, 4, fullChannelModeMask, offset);
SHAL_apply_bitmask(bdtr.reg, bdtr.main_output_enable_mask);
}
void Timer::setPWMDutyCycle(uint32_t dutyCycle) {
auto reg = getTimerCaptureCompareRegister(m_key);
SHAL_set_bits(reg.reg,16,dutyCycle,0);
}
Timer &TimerManager::get(Timer_Key timer_key) {
//Ensure that we don't try to get invalid timers
assert(timer_key != Timer_Key::S_TIM_INVALID && timer_key != Timer_Key::NUM_TIMERS);
Timer& selected = timers[static_cast<int>(timer_key)];
//Timer queried is not initialized yet (defaults to invalid)
if(selected.m_key == Timer_Key::S_TIM_INVALID){
timers[static_cast<int>(timer_key)] = Timer(timer_key); //Initialize TIMER_KEY
}
return timers[static_cast<int>(timer_key)];
}

16
SHAL/Src/STM32L4xx/Peripheral/Timer/SHAL_TIM_CALLBACK.cpp Normal file
View File

@@ -0,0 +1,16 @@
//
// Created by Luca on 8/28/2025.
//
#include "SHAL_TIM_CALLBACK.h"
DEFINE_TIMER_IRQ(Timer_Key::S_TIM1, TIM1_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM2, TIM2_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM6, TIM6_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM7, TIM7_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM15, TIM1_BRK_TIM15_IRQHandler)
DEFINE_TIMER_IRQ(Timer_Key::S_TIM16, TIM1_UP_TIM16_IRQHandler)
void registerTimerCallback(Timer_Key key, TimerCallback callback){
timer_callbacks[static_cast<uint32_t>(key)] = callback;
}

36
SHAL/Src/STM32F0XX/Peripheral/UART/SHAL_UART.cpp → SHAL/Src/STM32L4xx/Peripheral/UART/SHAL_UART.cpp
View File

@@ -10,9 +10,9 @@
#include "SHAL_UART.h"
#include "SHAL_GPIO.h"
void SHAL_UART::init(const UART_Pair pair){
void SHAL_UART::init(UART_Pair_Key pair){
m_UARTPair = pair;
m_key = pair;
SHAL_UART_Pair uart_pair = getUARTPair(pair); //Get the UART_PAIR information to be initialized
@@ -26,7 +26,7 @@ void SHAL_UART::init(const UART_Pair pair){
GET_GPIO(Tx_Key).setAlternateFunction(uart_pair.TxAlternateFunctionMask);
GET_GPIO(Rx_Key).setAlternateFunction(uart_pair.RxAlternateFunctionMask);
SHAL_UART_ENABLE_REG pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the SHAL_UART channel
SHAL_UART_Enable_Register pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the SHAL_UART channel
*pairUARTEnable.reg |= pairUARTEnable.mask; //Enable SHAL_UART line
@@ -35,31 +35,43 @@ void SHAL_UART::init(const UART_Pair pair){
void SHAL_UART::begin(uint32_t baudRate) volatile {
USART_TypeDef* usart = getUARTPair(m_UARTPair).USARTReg;
USART_TypeDef* usart = getUARTPair(m_key).USARTReg;
usart->CR1 &= ~USART_CR1_UE; //Disable USART
auto control_reg = getUARTControlRegister1(m_key);
SHAL_clear_bitmask(control_reg.reg, control_reg.usart_enable_mask); //Clear enable bit (turn off usart)
usart->CR1 = 0; //Clear USART config
usart->CR1 = USART_CR1_TE | USART_CR1_RE; //Tx enable and Rx Enable
SHAL_apply_bitmask(control_reg.reg, control_reg.transmit_enable_mask); //Enable Tx
SHAL_apply_bitmask(control_reg.reg, control_reg.receive_enable_mask); //Enable Rx
usart->BRR = 8000000 / baudRate; //MAKE SURE ANY FUNCTION THAT CHANGES CLOCK UPDATES THIS! //TODO DO NOT HARDCODE THIS SHIT
auto baud_rate_reg = getUARTBaudRateGenerationRegister(m_key);
usart->CR1 |= USART_CR1_UE;
uint32_t adjustedBaudRate = SystemCoreClock / baudRate;
SHAL_set_register_value(baud_rate_reg.reg,adjustedBaudRate);
SHAL_apply_bitmask(control_reg.reg, control_reg.usart_enable_mask); //Turn on usart
}
void SHAL_UART::sendString(const char *s) volatile {
while (*s) sendChar(*s++); //Send chars while we haven't reached end of s
while (*s) {//Send chars while we haven't reached end of s
sendChar(*s++);
}
}
void SHAL_UART::sendChar(char c) volatile {
USART_TypeDef* usart = getUARTPair(m_UARTPair).USARTReg;
auto ISR_non_fifo = getUARTISRFifoDisabled(m_key);
while(!(usart->ISR & USART_ISR_TXE)); //Wait for usart to finish what it's doing
if(!SHAL_WAIT_FOR_CONDITION_MS((*ISR_non_fifo.reg & ISR_non_fifo.transmit_data_register_empty_mask) != 0, 500)){
PIN(B3).setHigh();
return;
}
usart->TDR = c; //Send character
auto transmit_reg = getUARTTransmitDataRegister(m_key);
SHAL_set_register_value_16(transmit_reg.reg, static_cast<uint16_t>(c));
}

0
SHAL/Src/STM32L4XX/System/system_stm32l4xx.c → SHAL/Src/STM32L4xx/System/system_stm32l4xx.c
View File

4
SHAL/Src/Universal/syscalls.c
View File

@@ -1,8 +1,8 @@
/**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
* @author Auto-generated by STM32CubeMX
* @brief Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions

4
SHAL/Src/Universal/sysmem.c
View File

@@ -1,8 +1,8 @@
/**
******************************************************************************
* @file sysmem.c
* @author Generated by STM32CubeIDE
* @brief STM32CubeIDE System Memory calls file
* @author Generated by STM32CubeMX
* @brief System Memory calls file
*
* For more information about which C functions
* need which of these lowlevel functions

27
SHAL/Src/User_Config.h Normal file
View File

@@ -0,0 +1,27 @@
//
// Created by luca.lizaranzu on 3/20/2026.
//
#ifndef SHMINGO_HAL_USER_CONFIG_H
#define SHMINGO_HAL_USER_CONFIG_H
#include "SHAL.h"
//EDIT CONFIG HERE --------------------------------------------------------------------------------------------------------------------------------------------
constexpr int NUM_TIMER_GPIOS = 1;
constexpr int NUM_ADC_PINS = 2;
constexpr gpioTimerMap gpioTimerInfo[NUM_TIMER_GPIOS] = { //Add a GPIO config if you want to use it with a timer output (inverted channels not supported yet
{GPIO_Key::A3,"TIM2",SHAL_Timer_Channel::CH4, GPIO_Alternate_Function::AF1}
};
constexpr adcMap adcInfo[NUM_ADC_PINS] = {
{GPIO_Key::A1, SHAL_ADC_Channel::CH17},
{GPIO_Key::A3, SHAL_ADC_Channel::CH15},
};
//\\EDIT CONFIG HERE ------------------------------------------------------------------------------------------------------------------------------------------
#endif //SHMINGO_HAL_USER_CONFIG_H

97
SHAL/Src/main.cpp
View File

@@ -1,89 +1,42 @@
#include "SHAL.h"
#include "stm32f0xx.h"
#include <cstdlib>
void c3Interrupt(){
SHAL_UART2.sendString("Begin\r\n");
uint8_t cmd[3] = {0xAC, 0x33, 0x00};
SHAL_I2C1.masterWrite(0x38, cmd, 3);
SHAL_delay_ms(100);
uint8_t dht_buf[7] = {0};
//Read 7 bytes (status + 5 data + CRC)
SHAL_I2C1.masterRead(0x38, dht_buf, 7);
//Parse humidity (20 bits)
uint32_t rawHumidity = ((uint32_t)dht_buf[1] << 12) |
((uint32_t)dht_buf[2] << 4) |
((uint32_t)dht_buf[3] >> 4);
uint32_t rawTemp = (((uint32_t)dht_buf[3] & 0x0F) << 16) |
((uint32_t)dht_buf[4] << 8) |
((uint32_t)dht_buf[5]);
// Use 64-bit intermediate to avoid overflow
uint32_t hum_hundredths = (uint32_t)(((uint64_t)rawHumidity * 10000ULL) >> 20);
int32_t temp_hundredths = (int32_t)((((uint64_t)rawTemp * 20000ULL) >> 20) - 5000);
char out[80];
sprintf(out, "rawH=0x%05lX rawT=0x%05lX\r\n",
(unsigned long)rawHumidity, (unsigned long)rawTemp);
SHAL_UART2.sendString(out);
// print as X.YY
sprintf(out, "Temp: %ld.%02ld C, Hum: %ld.%02ld %%\r\n",
(long)(temp_hundredths / 100), (long)(abs(temp_hundredths % 100)),
(long)(hum_hundredths / 100), (long)(hum_hundredths % 100));
SHAL_UART2.sendString(out);
}
void tim2Handler(){
PIN(A4).toggle();
}
int main() {
SHAL_init();
//Setup UART2 (used by nucleo devices for USB comms)
SHAL_UART2.init(UART_Pair::Tx2A2_Rx2A3);
SHAL_UART2.begin(115200);
/*
PIN(A11).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
PIN(A11).setAlternateFunction(GPIO_Alternate_Function::AF2);
SHAL_TIM1.configurePWM(SHAL_Timer_Channel::CH4, 1000, 8000, 4000);
SHAL_TIM1.start();
*/
SHAL_I2C1.init(I2C_Pair::SCL1B6_SDA1B7);
SHAL_I2C1.setClockConfig(0x2000090E);
PIN(A11).setPinMode(PinMode::OUTPUT_MODE);
//Use pin C3 to trigger a function on external interrupt
PIN(C3).useAsExternalInterrupt(TriggerMode::RISING_EDGE,c3Interrupt);
//PIN(B4).setPinMode(PinMode::OUTPUT_MODE);
//PIN(B4).setHigh();
SHAL_TIM2.init(8000-1,1500-1);
SHAL_TIM2.setCallbackFunc(tim2Handler);
SHAL_TIM2.start();
RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
PIN(A4).setPinMode(PinMode::OUTPUT_MODE);
PIN(A5).setPinMode(PinMode::OUTPUT_MODE);
/* Small delay to ensure clock is stable (optional but safe) */
for (volatile int i = 0; i < 1000; i++);
SHAL_delay_ms(3000); //Wait 100 ms from datasheet
/* 2. Set PB4 as general purpose output */
// MODER: 2 bits per pin → pin 4 → bits [9:8]
GPIOB->MODER &= ~(3U << (4 * 2)); // Clear mode bits
GPIOB->MODER |= (1U << (4 * 2)); // Set as output (01)
uint8_t cmd = 0x71;
uint8_t status = 0;
/* 3. Set PB4 HIGH */
GPIOB->BSRR = (1U << 4); // Atomic set
SHAL_I2C1.masterWriteRead(0x38, &cmd, 1, &status, 1);
char statusString[32];
sprintf(statusString, "Status = 0x%02X\r\n", status);
SHAL_UART2.sendString(statusString);
SHAL_delay_ms(10);
c3Interrupt();
//End setup
PIN(A11).setHigh();
while (true) {
__WFI();
PIN(A11).toggle();
SHAL_delay_us(10);
PIN(A11).toggle();
}
}

8
gcc-arm-none-eabi.cmake
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@@ -3,14 +3,14 @@ set(CMAKE_SYSTEM_PROCESSOR arm)
set(TOOLCHAIN_PREFIX arm-none-eabi-)
set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc)
set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++)
set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}gcc)
set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc.exe)
set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++.exe)
set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}gcc.exe)
set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy)
set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size)
set(COMMON_FLAGS "-mcpu=cortex-m0 -mthumb -fdata-sections -ffunction-sections")
set(COMMON_FLAGS "-mcpu=cortex-m7 -mthumb -fdata-sections -ffunction-sections")
set(CMAKE_C_FLAGS_INIT "${COMMON_FLAGS} --specs=nano.specs")
set(CMAKE_CXX_FLAGS_INIT "${COMMON_FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics --specs=nano.specs")

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shmingo-HAL.hex Normal file
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