test

H7 working
Test program done
2026-04-02 14:09:53 -07:00 · 2026-04-01 14:11:41 -07:00 · 2026-03-20 11:41:44 -07:00 · 2026-03-16 17:10:48 -07:00
26 changed files with 1591 additions and 138 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -7,17 +7,16 @@ set(PROJECT_DIR ${CMAKE_CURRENT_SOURCE_DIR})

 enable_language(C ASM CXX)

-set(MCU_FAMILY "STM32H7xx")
-set(MCU_MODEL "STM32H753xx")
+set(MCU_FAMILY "STM32F0xx")
+set(MCU_MODEL "STM32F072xB")

 set(CPU_PARAMETERS
-        -mcpu=cortex-m7
-        -mfpu=fpv5-d16
-        -mfloat-abi=hard
+        -mcpu=cortex-m0
 )

-set(STARTUP_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/H753ZIT6/startup_stm32h753xx.S)
-set(MCU_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/H753ZIT6/stm32h753zitx_flash.ld)
+set(STARTUP_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/F030x6/startup_stm32f030x6.S
+        SHAL/Src/User_Config.h)
+set(MCU_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/MX/F030x6/STM32F030XX_FLASH.ld)

 set(EXECUTABLE ${CMAKE_PROJECT_NAME})
 enable_language(C CXX ASM)
@@ -37,12 +36,9 @@ set(PROJECT_INCLUDE_DIRECTORIES
        ${CMAKE_CURRENT_SOURCE_DIR}

        #[[
-SHAL/Include/Peripheral/UART
-SHAL/Include/Peripheral/UART/Reg
+
 SHAL/Include/Peripheral/I2C
 SHAL/Include/Peripheral/I2C/Reg
-SHAL/Include/Peripheral/ADC
-SHAL/Include/Peripheral/ADC/Reg
 SHAL/Include/Peripheral/EXT
 SHAL/Include/Peripheral/EXT/Reg
 ]]#
@@ -51,6 +47,7 @@ SHAL/Include/Peripheral/EXT/Reg
        SHAL/Include/Peripheral/GPIO/Reg
        SHAL/Include/Peripheral/Timer
        SHAL/Include/Peripheral/Timer/Reg
+        SHAL/Src
        ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include
 )

--- a/MX/F030x6/STM32F030XX_FLASH.ld
+++ b/MX/F030x6/STM32F030XX_FLASH.ld
@@ -0,0 +1,249 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: STM32CubeMX
+**
+**  Abstract    : Linker script for STM32F030K6Tx series
+**                32Kbytes FLASH and 4Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2025 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 4K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 32K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+  } >RAM AT> FLASH
+
+ /* Initialized TLS data section */
+  .tdata : ALIGN(4)
+  {
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+    PROVIDE(__data_end = .);
+    PROVIDE(__tdata_end = .);
+  } >RAM AT> FLASH
+
+  PROVIDE( __tdata_start = ADDR(.tdata) );
+  PROVIDE( __tdata_size = __tdata_end - __tdata_start );
+
+  PROVIDE( __data_start = ADDR(.data) );
+  PROVIDE( __data_size = __data_end - __data_start );
+
+  PROVIDE( __tdata_source = LOADADDR(.tdata) );
+  PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+  PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source );
+
+  PROVIDE( __data_source = LOADADDR(.data) );
+  PROVIDE( __data_source_end = __tdata_source_end );
+  PROVIDE( __data_source_size = __data_source_end - __data_source );
+  /* Uninitialized data section */
+  .tbss (NOLOAD) : ALIGN(4)
+  {
+     /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.tbss .tbss.*)
+    . = ALIGN(4);
+    PROVIDE( __tbss_end = . );
+  } >RAM
+
+  PROVIDE( __tbss_start = ADDR(.tbss) );
+  PROVIDE( __tbss_size = __tbss_end - __tbss_start );
+  PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+
+  PROVIDE( __tls_base = __tdata_start );
+  PROVIDE( __tls_end = __tbss_end );
+  PROVIDE( __tls_size = __tls_end - __tls_base );
+  PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+  PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) );
+  PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+  PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+  .bss (NOLOAD) : ALIGN(4)
+  {
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+      . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+      PROVIDE( __bss_end = .);
+  } >RAM
+  PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+
+  PROVIDE( __bss_start = __tbss_start );
+  PROVIDE( __bss_size = __bss_end - __bss_start );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack (NOLOAD) :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a:* ( * )
+    libm.a:* ( * )
+    libgcc.a:* ( * )
+  }
+
+}
--- a/MX/F030x6/startup_stm32f030x6.s
+++ b/MX/F030x6/startup_stm32f030x6.s
@@ -0,0 +1,258 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f030x6.s
+  * @author    MCD Application Team
+  * @brief     STM32F030x4/STM32F030x6 devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+  
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler                   /* Window WatchDog              */
+  .word  0                                 /* Reserved                     */
+  .word  RTC_IRQHandler                    /* RTC through the EXTI line    */
+  .word  FLASH_IRQHandler                  /* FLASH                        */
+  .word  RCC_IRQHandler                    /* RCC                          */
+  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word  0                                 /* Reserved                     */
+  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word  DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */
+  .word  ADC1_IRQHandler                   /* ADC1                         */
+  .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */
+  .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word  0                                 /* Reserved                     */
+  .word  TIM3_IRQHandler                   /* TIM3                         */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  TIM14_IRQHandler                  /* TIM14                        */
+  .word  0                                 /* Reserved                     */
+  .word  TIM16_IRQHandler                  /* TIM16                        */
+  .word  TIM17_IRQHandler                  /* TIM17                        */
+  .word  I2C1_IRQHandler                   /* I2C1                         */
+  .word  0                                 /* Reserved                     */
+  .word  SPI1_IRQHandler                   /* SPI1                         */
+  .word  0                                 /* Reserved                     */
+  .word  USART1_IRQHandler                 /* USART1                       */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak      RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak      EXTI0_1_IRQHandler
+  .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+  .weak      EXTI2_3_IRQHandler
+  .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+  .weak      EXTI4_15_IRQHandler
+  .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel2_3_IRQHandler
+  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel4_5_IRQHandler
+  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+  .weak      ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak      TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak      TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak      TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+
+
--- a/4
+++ b/4
@@ -6,8 +6,8 @@ BUILD_TYPE   ?= Debug
 TOOLCHAIN    := gcc-arm-none-eabi.cmake

 # MCU target (override on command line: make build MCU_MODEL=STM32F051x8)
-MCU_MODEL    ?= STM32H753xx
-MCU_FAMILY   ?= STM32H7xx
+MCU_MODEL    ?= STM32F072xB
+MCU_FAMILY   ?= STM32F0xx

 # --- Default target ---
 all: build
--- a/SHAL/Include/Core/SHAL_CORE.h
+++ b/SHAL/Include/Core/SHAL_CORE.h
@@ -76,12 +76,22 @@ bool SHAL_wait_for_condition_ms(Condition cond, uint32_t timeout_ms) {
    return false; // timeout
 }

+bool SHAL_check_bit(const volatile uint32_t* reg, uint32_t mask);
+
+bool SHAL_wait_for_bit_set_us(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
+
+bool SHAL_wait_for_bit_clear_us(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
+
+bool SHAL_wait_for_bit_set_ms(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
+
+bool SHAL_wait_for_bit_clear_ms(const volatile uint32_t* reg, uint32_t mask, uint16_t timeout);
+


 #define SHAL_set_bits(reg, size, bits, offset)                    \
    do {                                                          \
        if ((reg) != NULL) {                                      \
-            uint32_t _mask = ((1U << (size)) - 1U);               \
+            uint32_t _mask = (size == 32) ? 0xFFFFFFFFU : ((1U << (size)) - 1U);               \
            *(reg) &= ~((uint32_t)(_mask) << (offset));           \
            *(reg) |= ((uint32_t)(bits) << (offset));             \
        }                                                         \
@@ -115,6 +125,13 @@ bool SHAL_wait_for_condition_ms(Condition cond, uint32_t timeout_ms) {
        *(reg) |= (mask);                                         \
    } while (0)

+#define SHAL_clear_register_value(reg)                            \
+    do {                                                          \
+        if ((reg) != NULL) {                                      \
+            *(reg) = 0;                                           \
+        }                                                         \
+    } while (0)
+
 #define SHAL_set_register_value(reg, value)                       \
    do {                                                          \
        if ((reg) != NULL) {                                      \
--- a/SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_H753ZI.h
+++ b/SHAL/Include/Peripheral/ADC/Reg/SHAL_ADC_REG_H753ZI.h
@@ -0,0 +1,213 @@
+//
+// Created by Luca on 10/8/2025.
+//
+
+#ifndef SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H
+#define SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H
+
+#include "SHAL_CORE.h"
+#include "SHAL_ADC_TYPES.h"
+#include "stm32h753xx.h"
+
+#define SHAL_ADC1 SHAL_ADC(1)
+#define SHAL_ADC2 SHAL_ADC(2)
+#define SHAL_ADC3 SHAL_ADC(3)
+
+#define NUM_ADCS 3
+#define NUM_ADC_CHANNELS 16
+
+enum class SHAL_ADC_Channel : uint32_t {
+    CH0 = 0,
+    CH1,
+    CH2,
+    CH3,
+    CH4,
+    CH5,
+    CH6,
+    CH7,
+    CH8,
+    CH9,
+    CH10,
+    CH11,
+    CH12,
+    CH13,
+    CH14,
+    CH15,
+    CH16,
+    CH17,
+    CH18,
+    CHTemp,
+    CHRef,
+    CHBat,
+    NO_ADC_MAPPING
+};
+
+enum class ADC_Key : uint8_t{
+    S_ADC1 = 0,
+    S_ADC2 = 1,
+    S_ADC3 = 2,
+    NUM_ADC = 3,
+    INVALID = 255
+};
+
+enum class SHAL_ADC_Resolution : uint8_t { //TODO figure out what to do with this difference
+    B16         = 0x00,
+    B14         = 0x01,
+    B12         = 0x02,
+    B10         = 0x03,
+    B8          = 0x04,
+    B6          = 0x05,
+};
+
+enum class SHAL_ADC_Clock_Mode {
+    ASYNC = 0x00,
+    SYNC_BY_1 = 0x01,
+    SYNC_BY_2 = 0x02,
+    SYNC_BY_4 = 0x03,
+};
+
+
+static volatile ADC_TypeDef* ADC_TABLE[3] = { //Lookup table for ADCs
+    ADC1,
+    ADC2,
+    ADC3,
+};
+
+static volatile ADC_Common_TypeDef* ADC_CCR_TABLE[3] = { //Common registers
+    ADC12_COMMON, //1 and 2 share a common register
+    ADC12_COMMON,
+    ADC3_COMMON,
+};
+
+enum class ADC_Clock_Source : uint32_t {
+    SHAL_NO_CLOCK       = 0x00,
+    SHAL_PLLSAI1        = 0x01,
+    SHAL_PLLSYS         = 0x02,
+    SHAL_SYSCLK         = 0x03,
+};
+
+static SHAL_ADC_Common_Control_Reg getADCCommonControl(ADC_Key key) {
+
+    SHAL_ADC_Common_Control_Reg res = {
+        .reg = nullptr,
+        .VoltageRefEnable = ADC_CCR_VREFEN,
+        .TempSensorEnable = ADC_CCR_TSEN,
+        .VBatteryEnable = ADC_CCR_VBATEN,
+        .clock_mode_position = ADC_CCR_CKMODE_Pos
+    };
+
+    res.reg = &ADC_CCR_TABLE[static_cast<uint8_t>(key)]->CCR;
+    return res;
+}
+
+static inline SHAL_ADC_RCC_Enable_Reg getADCRCCEnableRegister(const ADC_Key key){
+    switch (key) {
+        case ADC_Key::S_ADC1:
+        case ADC_Key::S_ADC2:
+            return {&RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN};
+        case ADC_Key::S_ADC3:
+            return {&RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN};
+        default:
+            __builtin_unreachable();
+    }
+}
+
+static inline SHAL_ADC_Control_Reg getADCControlReg(ADC_Key key) {
+
+    SHAL_ADC_Control_Reg res = {nullptr, ADC_CR_ADEN,
+                                ADC_CR_ADSTP,
+                                ADC_CR_ADDIS,
+                                ADC_CR_ADCAL,
+                                ADC_CR_ADSTART,
+                                ADC_CR_DEEPPWD,
+                                 ADC_CR_ADVREGEN,
+                                 ADC_CR_ADCALDIF};
+
+    res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CR);
+    return res;
+}
+
+static inline SHAL_ADC_Config_Reg getADCConfigReg(ADC_Key key) {
+
+    //NOTE offset of 33 means the function is deprecated
+    SHAL_ADC_Config_Reg res = {nullptr,
+        ADC_CFGR_CONT,
+        ADC_CFGR_RES_Pos,
+        0,  //TODO 0 is broken, shouldnt have alignment
+        ADC_CFGR_CONT_Msk
+    };
+
+    res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->CFGR);
+    return res;
+}
+
+static inline SHAL_ADC_ISR_Reg getADCISRReg(ADC_Key key){
+    SHAL_ADC_ISR_Reg res = {nullptr,
+        ADC_ISR_EOC,
+        ADC_ISR_EOS,
+        ADC_ISR_ADRDY,
+        ADC_ISR_OVR,
+    ADC_ISR_LDORDY};
+
+    res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->ISR);
+    return res;
+}
+
+static inline SHAL_ADC_Data_Reg getADCDataReg(ADC_Key key){
+    SHAL_ADC_Data_Reg res = {nullptr, 0xFFFF};
+
+    res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->DR);
+    return res;
+}
+
+static inline SHAL_ADC_Channel_Sampling_Time_Reg getADCChannelSamplingTimeRegister(ADC_Key key, SHAL_ADC_Channel channel){
+    volatile ADC_TypeDef* ADCReg = ADC_TABLE[static_cast<uint8_t>(key)];
+
+    volatile uint32_t* SMPReg = nullptr;
+    uint32_t pos;
+
+    auto channelNum = static_cast<uint8_t>(channel);
+
+    if (channelNum <= 9) {
+        SMPReg = &ADCReg->SMPR1;
+        pos = (channelNum * 3);
+    } else {
+        SMPReg = &ADCReg->SMPR2;
+        pos = ((channelNum - 10) * 3);
+    }
+
+    return {SMPReg, pos};
+}
+
+static inline SHAL_ADC_Sequence_Amount_Reg getADCSequenceAmountRegister(ADC_Key key){
+    SHAL_ADC_Sequence_Amount_Reg res = {nullptr, ADC_SQR1_L_Pos};
+
+    res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->SQR1);
+    return res;
+}
+
+static SHAL_ADC_Sequence_Reg getADCSequenceRegister(ADC_Key key, uint32_t conversionNum){
+
+    volatile ADC_TypeDef* adc_reg = ADC_TABLE[static_cast<uint8_t>(key)];
+
+    volatile uint32_t* sqr[4] = {&adc_reg->SQR1,
+                                 &adc_reg->SQR2,
+                                 &adc_reg->SQR3,
+                                 &adc_reg->SQR4,
+    };
+
+    const uint8_t sqrIndex = conversionNum / 5; //CONVERSION NUM STARTS AT 1! AS PER DATASHEET REFERENCING IT AS SQ1
+    const uint32_t offset = (((conversionNum) % 5) * 6);
+
+    return {sqr[sqrIndex], offset};
+}
+
+static SHAL_ADC_Preselect_Reg getADCPreselectRegister(ADC_Key key, SHAL_ADC_Channel channel) {
+    SHAL_ADC_Preselect_Reg res = {nullptr, static_cast<uint32_t>(channel)};
+
+    res.reg = &(ADC_TABLE[static_cast<uint8_t>(key)]->PCSEL);
+
+    return res;
+}
+
+#endif //SHMINGO_HAL_SHAL_ADC_REG_H753ZI_H
--- a/SHAL/Include/Peripheral/ADC/SHAL_ADC.h
+++ b/SHAL/Include/Peripheral/ADC/SHAL_ADC.h
@@ -16,19 +16,21 @@ class SHAL_ADC {

 public:

-    SHAL_Result init(ADC_Key key);
+    SHAL_Result init(ADC_Key key, SHAL_ADC_Sample_Mode mode);

-    SHAL_Result calibrate();
+    SHAL_Result calibrate(SHAL_ADC_Sample_Mode sampleMode) const;

-    SHAL_Result configureResolution(SHAL_ADC_Resolution resolution);
+    SHAL_Result configureResolution(SHAL_ADC_Resolution resolution) const;

-    SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment);
+    SHAL_Result configureAlignment(SHAL_ADC_Alignment alignment) const;
+
+    SHAL_Result preselectChannel(SHAL_ADC_Channel channel) const;

    /// Performs analog to digital conversion on a single channel, one time
    /// \param channel Channel to be converted
    /// \param time SHAL_ADC_SampleTime - amount of clock cycles per conversion
    /// \return resulting value
-    uint16_t singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8);
+    uint32_t singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time = SHAL_ADC_SampleTime::C8) const;

    /// Performs analog to digital conversion on multiple channels, one time
    /// \param channels Pointer to an array of channels to convert
@@ -46,29 +48,29 @@ private:
    ADC_Key m_ADCKey = ADC_Key::INVALID;

    //Checks to see if instance is initialized with a proper ADC peripheral tag
-    bool isValid();
+    bool isValid() const;

    //Enabled peripheral
-    SHAL_Result enable();
+    SHAL_Result enable() const;

    //Disables peripheral
-    SHAL_Result disable();
+    SHAL_Result disable() const;

    //Wake up ADC from initial deep sleep state
-    SHAL_Result wakeFromDeepSleep();
+    SHAL_Result wakeFromDeepSleep() const;

-    SHAL_Result startConversion();
+    SHAL_Result startConversion() const;

    /// Adds an ADC channel to the conversion sequence
    /// \param channel Channel to add
-    /// \param index Index to add channel to (ADC channel will be the nth channel to convert
+    /// \param conversionNumber Index to add channel to (ADC channel will be the nth channel to convert
    /// \return Result
-    SHAL_Result addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t index);
+    SHAL_Result addADCChannelToSequence(SHAL_ADC_Channel channel, uint32_t conversionNumber) const;

    /// Sets the amount of ADC channels to convert
    /// \param amount Number of channels to convert
    /// \return
-    SHAL_Result setADCSequenceAmount(uint32_t amount);
+    SHAL_Result setADCSequenceAmount(uint32_t amount) const;

 };

@@ -83,7 +85,6 @@ public:

    static SHAL_ADC& getByIndex(int index);

-
    ADCManager() = delete;

 private:
--- a/SHAL/Include/Peripheral/ADC/SHAL_ADC_REG.h
+++ b/SHAL/Include/Peripheral/ADC/SHAL_ADC_REG.h
@@ -88,6 +88,50 @@
 #elif defined(STM32L4S7xx)
  #include "stm32l4s7xx.h"
 #elif defined(STM32L4S9xx)
+#elif defined(STM32H743xx)
+  #include "stm32h743xx.h"
+#elif defined(STM32H753xx)
+  #include "SHAL_ADC_REG_H753ZI.h"
+#elif defined(STM32H750xx)
+  #include "stm32h750xx.h"
+#elif defined(STM32H742xx)
+  #include "stm32h742xx.h"
+#elif defined(STM32H745xx)
+  #include "stm32h745xx.h"
+#elif defined(STM32H745xG)
+  #include "stm32h745xg.h"
+#elif defined(STM32H755xx)
+  #include "stm32h755xx.h"
+#elif defined(STM32H747xx)
+  #include "stm32h747xx.h"
+#elif defined(STM32H747xG)
+  #include "stm32h747xg.h"
+#elif defined(STM32H757xx)
+  #include "stm32h757xx.h"
+#elif defined(STM32H7B0xx)
+  #include "stm32h7b0xx.h"
+#elif defined(STM32H7B0xxQ)
+  #include "stm32h7b0xxq.h"
+#elif defined(STM32H7A3xx)
+  #include "stm32h7a3xx.h"
+#elif defined(STM32H7B3xx)
+  #include "stm32h7b3xx.h"
+#elif defined(STM32H7A3xxQ)
+  #include "stm32h7a3xxq.h"
+#elif defined(STM32H7B3xxQ)
+  #include "stm32h7b3xxq.h"
+#elif defined(STM32H735xx)
+  #include "stm32h735xx.h"
+#elif defined(STM32H733xx)
+  #include "stm32h733xx.h"
+#elif defined(STM32H730xx)
+  #include "stm32h730xx.h"
+#elif defined(STM32H730xxQ)
+  #include "stm32h730xxq.h"
+#elif defined(STM32H725xx)
+  #include "stm32h725xx.h"
+#elif defined(STM32H723xx)
+  #include "stm32h723xx.h"
 #else
 #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
 #endif
--- a/SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
+++ b/SHAL/Include/Peripheral/ADC/SHAL_ADC_TYPES.h
@@ -5,12 +5,15 @@
 #ifndef SHMINGO_HAL_SHAL_ADC_TYPES_H
 #define SHMINGO_HAL_SHAL_ADC_TYPES_H

+#include "SHAL_CORE.h"
+
 //Common register among all ADC peripherals
 struct SHAL_ADC_Common_Control_Reg {
    volatile uint32_t* reg;
    uint32_t VoltageRefEnable;
    uint32_t TempSensorEnable;
    uint32_t VBatteryEnable;
+    uint32_t clock_mode_position;
 };

 //Register controlling the ADC peripheral clock
@@ -29,7 +32,7 @@ struct SHAL_ADC_Control_Reg {
    uint32_t start_mask;
    uint32_t deep_power_down_mask;
    uint32_t voltage_regulator_mask;
-    uint32_t differential_mode_mask;
+    uint32_t sample_mode_offset;
 };

 //Register controlling ADC configuration
@@ -55,6 +58,7 @@ struct SHAL_ADC_ISR_Reg {
    uint32_t end_of_sequence_mask;
    uint32_t ready_mask;
    uint32_t overrun_mask;
+    uint32_t ldo_ready_mask;
 };

 //Register controlling the clock source for the ADC
@@ -79,9 +83,13 @@ struct SHAL_ADC_Sequence_Amount_Reg {
 *reg 1 + offset 1
 *Any sections after the last one (for example, max for a 16 channel register is reg 4 offset 2*/
 struct SHAL_ADC_Sequence_Reg {
-    volatile uint32_t* regs[6];
+    volatile uint32_t* reg;
+    uint32_t sequence_offset;
+};

-    uint32_t offsets[5];
+struct SHAL_ADC_Preselect_Reg {
+    volatile uint32_t* reg;
+    uint32_t channel_offset;
 };


@@ -98,16 +106,14 @@ enum class SHAL_ADC_SampleTime : uint32_t {
    C8          = 0x07  //239.5 cycles
 };

-enum class SHAL_ADC_Resolution : uint8_t {
-    B12         = 0x00,
-    B10         = 0x01,
-    B8          = 0x02,
-    B6          = 0x03,
-};
-
 enum class SHAL_ADC_Alignment : uint8_t {
    RIGHT       = 0x00,
    LEFT        = 0x01,
 };

+enum class SHAL_ADC_Sample_Mode {
+    SINGLE_ENDED = 0,
+    DIFFERENTIAL = 1,
+};
+
 #endif //SHMINGO_HAL_SHAL_ADC_TYPES_H
--- a/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
+++ b/SHAL/Include/Peripheral/GPIO/SHAL_GPIO.h
@@ -17,31 +17,33 @@ class SHAL_GPIO{

 public:

-    void toggle() volatile;
+    void toggle() const volatile;

    //TODO replace stupid offset hack from APB
-    void setHigh();
-    void setLow();
+    void setHigh() const;
+    void setLow() const;

    /// Uses the ADC to read an analog voltage value
    /// \param sampleTime The amount of clock cycles to use for the ADC
    /// \return ADC result
    //uint16_t analogRead(SHAL_ADC_SampleTime sampleTime = SHAL_ADC_SampleTime::C8); TODO Reimplement

-    uint16_t digitalRead();
+    uint16_t digitalRead() const;

-    void setAlternateFunction(GPIO_Alternate_Function AF) volatile;
+    void setAlternateFunction(GPIO_Alternate_Function AF) const volatile;
    //void setAlternateFunction(GPIO_Alternate_Function_Mapping AF) volatile; //TODO reimplement?

-    void setOutputType(PinType type) volatile;
+    void setOutputType(PinType type) const volatile;

-    void setOutputSpeed(OutputSpeed speed) volatile;
+    void setOutputSpeed(OutputSpeed speed) const volatile;

-    void setInternalResistor(InternalResistorType type) volatile;
+    void setInternalResistor(InternalResistorType type) const volatile;

    //void useAsExternalInterrupt(TriggerMode mode, EXTICallback callback); TODO reimplement

-    SHAL_Result setPinMode(PinMode mode) volatile;
+    SHAL_Result setPinMode(PinMode mode) const volatile;
+
+    [[nodiscard]] GPIO_Key getKey() const {return m_GPIO_KEY;};

 private:

@@ -73,6 +75,9 @@ class GPIOManager{
 public:

    static SHAL_GPIO& get(GPIO_Key);
+    static SHAL_GPIO& get(uint8_t portNum, uint8_t pinNum);
+
+    static void initGPIO(GPIO_Key key);

    //static SHAL_ADC getGPIOADC(){ return m_GPIO_ADC;} TODO Reimplement

--- a/SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_H753xx.h
+++ b/SHAL/Include/Peripheral/Timer/Reg/SHAL_TIM_REG_H753xx.h
@@ -19,8 +19,13 @@ enum class Timer_Key : uint8_t { //For STM32F072
    S_TIM1 = 0,
    S_TIM2 = 1,
    S_TIM3 = 2,
+    S_TIM4,
+    S_TIM5,
    S_TIM6,
    S_TIM7,
+    S_TIM8,
+    S_TIM12,
+    S_TIM13,
    S_TIM14,
    S_TIM15,
    S_TIM16,
@@ -32,19 +37,29 @@ enum class Timer_Key : uint8_t { //For STM32F072
 #define SHAL_TIM1 TimerManager::get(Timer_Key::S_TIM1)
 #define SHAL_TIM2 TimerManager::get(Timer_Key::S_TIM2)
 #define SHAL_TIM3 TimerManager::get(Timer_Key::S_TIM3)
+#define SHAL_TIM4 TimerManager::get(Timer_Key::S_TIM4)
+#define SHAL_TIM5 TimerManager::get(Timer_Key::S_TIM5)
 #define SHAL_TIM6 TimerManager::get(Timer_Key::S_TIM6)
 #define SHAL_TIM7 TimerManager::get(Timer_Key::S_TIM7)
+#define SHAL_TIM8 TimerManager::get(Timer_Key::S_TIM8)
+#define SHAL_TIM12 TimerManager::get(Timer_Key::S_TIM12)
+#define SHAL_TIM13 TimerManager::get(Timer_Key::S_TIM13)
 #define SHAL_TIM14 TimerManager::get(Timer_Key::S_TIM14)
 #define SHAL_TIM15 TimerManager::get(Timer_Key::S_TIM15)
 #define SHAL_TIM16 TimerManager::get(Timer_Key::S_TIM16)
 #define SHAL_TIM17 TimerManager::get(Timer_Key::S_TIM17)

-static SHAL_TIM_Info TIM_INFO_TABLE[9] = {
+static SHAL_TIM_Info TIM_INFO_TABLE[14] = {
        {TIM1,TIM1_TRG_COM_IRQn,4},
        {TIM2,TIM2_IRQn,4},
        {TIM3,TIM3_IRQn,4},
+        {TIM3,TIM4_IRQn,4},
+        {TIM3,TIM5_IRQn,4},
        {TIM6,TIM6_DAC_IRQn,0},
        {TIM7,TIM7_IRQn,0},
+        {TIM8,TIM8_TRG_COM_TIM14_IRQn,6},
+        {TIM12,TIM8_BRK_TIM12_IRQn,2},
+        {TIM13,TIM8_UP_TIM13_IRQn,1},
        {TIM14,TIM8_TRG_COM_TIM14_IRQn,1},
        {TIM15,TIM15_IRQn,2},
        {TIM16,TIM16_IRQn,1},
@@ -67,9 +82,14 @@ static SHAL_TIM_RCC_Register getTimerRCC(Timer_Key t) {
        case Timer_Key::S_TIM1:  return {&RCC->APB2ENR, RCC_APB2ENR_TIM1EN};
        case Timer_Key::S_TIM2:  return {&RCC->APB1LENR, RCC_APB1LENR_TIM2EN};
        case Timer_Key::S_TIM3:  return {&RCC->APB1LENR, RCC_APB1LENR_TIM3EN};
+        case Timer_Key::S_TIM4:  return {&RCC->APB1LENR, RCC_APB1LENR_TIM4EN};
+        case Timer_Key::S_TIM5:  return {&RCC->APB1LENR, RCC_APB1LENR_TIM5EN};
        case Timer_Key::S_TIM6:  return {&RCC->APB1LENR, RCC_APB1LENR_TIM6EN};
        case Timer_Key::S_TIM7:  return {&RCC->APB1LENR, RCC_APB1LENR_TIM7EN};
-        case Timer_Key::S_TIM14: return {&RCC->APB1LENR, RCC_APB1LENR_TIM14EN};
+        case Timer_Key::S_TIM8:  return {&RCC->APB1LENR, RCC_APB2ENR_TIM8EN};
+        case Timer_Key::S_TIM14: return {&RCC->APB1LENR, RCC_APB1LENR_TIM12EN};
+        case Timer_Key::S_TIM12: return {&RCC->APB1LENR, RCC_APB1LENR_TIM13EN};
+        case Timer_Key::S_TIM13: return {&RCC->APB1LENR, RCC_APB1LENR_TIM14EN};
        case Timer_Key::S_TIM15: return {&RCC->APB2ENR, RCC_APB2ENR_TIM15EN};
        case Timer_Key::S_TIM16: return {&RCC->APB2ENR, RCC_APB2ENR_TIM16EN};
        case Timer_Key::S_TIM17: return {&RCC->APB2ENR, RCC_APB2ENR_TIM17EN};
--- a/SHAL/Include/Peripheral/Timer/SHAL_TIM.h
+++ b/SHAL/Include/Peripheral/Timer/SHAL_TIM.h
@@ -21,18 +21,19 @@ public:
    /// Initializes a timer
    /// \param prescaler The amount of times the base clock has to cycle before the timer adds one to the count
    /// \param autoReload The number of timer counts before the count is reset and IRQ is called
-    void init(uint16_t prescaler, uint16_t autoReload);
+    void init(uint32_t prescaler, uint32_t autoReload);
+    void init() const; //Empty init (enable RCC)

    /// Simple function to set a timer in basic PWM mode
    /// @param channel Channel to output on
    /// @param prescaler Divider from sysclock
    /// @param autoReload Counter value to reset at
    /// @param captureCompareThreshold PWM trigger value (duty cycle = this / autoReload)
-    void configurePWM(SHAL_Timer_Channel channel, uint16_t prescaler, uint16_t autoReload, uint16_t captureCompareThreshold);
+    void configurePWM(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold);



-    void configureOneshot(SHAL_Timer_Channel channel, uint16_t prescaler, uint16_t autoReload, uint16_t captureCompareThreshold);
+    void configureOneshot(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold);

    //Starts the counter
    void start();
@@ -41,18 +42,20 @@ public:
    void stop() const;

    //Set prescaler value
-    void setPrescaler(uint16_t presc) const;
+    void setPrescaler(uint32_t presc) const;

    //Set auto reload register
-    void setARR(uint16_t arr) const;
+    void setARR(uint32_t arr) const;

    //Enable interrupts
    void enableInterrupt();

    //Capture Compare Functions
-    void setCaptureCompareValue(SHAL_Timer_Channel channel, uint16_t value);
+    void setCaptureCompareValue(SHAL_Timer_Channel channel, uint32_t value) const;
+
    void enableChannel(SHAL_Timer_Channel channel, SHAL_Timer_Channel_Main_Output_Mode mainOutputMode, SHAL_Timer_Channel_Complimentary_Output_Mode complimentaryOutputMode);
-    void setOutputCompareMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode);
+
+    void setOutputCompareMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode) const;

    //Set TIMER_KEY IRQ callback function
    void setCallbackFunc(TimerCallback callback) const {
--- a/SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_H753ZI.h
+++ b/SHAL/Include/Peripheral/UART/Reg/SHAL_UART_REG_H753ZI.h
@@ -0,0 +1,113 @@
+//
+// Created by Luca on 9/7/2025.
+//
+
+#ifndef SHAL_UART_REG_F072XB_H
+#define SHAL_UART_REG_F072XB_H
+
+#include <stm32h753xx.h>
+#include <cassert>
+
+#include "SHAL_UART_TYPES.h"
+
+#define NUM_USART_LINES 4
+
+#define SHAL_UART1 UART(1)
+#define SHAL_UART2 UART(2)
+#define SHAL_UART3 UART(3)
+#define SHAL_UART4 UART(4)
+
+//Valid usart Tx and Rx pairings for STM32F072
+enum class UART_Pair_Key : uint8_t{
+    //UART2
+    Tx2A2_Rx2A3,
+    Tx3D8_Rx3D9,
+
+    NUM_PAIRS,
+    INVALID
+};
+
+static SHAL_UART_Pair getUARTPair(const UART_Pair_Key pair){
+    switch(pair){
+        case UART_Pair_Key::Tx2A2_Rx2A3:
+            return {USART2, GPIO_Key::A2, GPIO_Key::A3, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
+        case UART_Pair_Key::Tx3D8_Rx3D9:
+            return {USART3, GPIO_Key::D8, GPIO_Key::D9, GPIO_Alternate_Function::AF7, GPIO_Alternate_Function::AF7};
+        case UART_Pair_Key::NUM_PAIRS:
+        case UART_Pair_Key::INVALID:
+            assert(false);
+            return {nullptr, GPIO_Key::INVALID, GPIO_Key::INVALID, GPIO_Alternate_Function::AF0, GPIO_Alternate_Function::AF0};
+        default:
+            __builtin_unreachable();
+    }
+}
+
+constexpr SHAL_UART_Enable_Register getUARTEnableReg(const UART_Pair_Key pair){
+    switch(pair){
+        case UART_Pair_Key::Tx2A2_Rx2A3:
+            return {&RCC->APB1LENR,RCC_APB1LENR_USART2EN};
+        case UART_Pair_Key::Tx3D8_Rx3D9:
+            return {&RCC->APB1LENR,RCC_APB1LENR_USART3EN};
+        case UART_Pair_Key::NUM_PAIRS:
+        case UART_Pair_Key::INVALID:
+            assert(false);
+            return {nullptr, 0};
+    }
+    __builtin_unreachable();
+}
+
+static SHAL_UART_Control_Register_1 getUARTControlRegister1(const UART_Pair_Key key) {
+    SHAL_UART_Control_Register_1 res = {
+        nullptr,
+        USART_CR1_UE,
+        USART_CR1_TE,
+        USART_CR1_RE,
+        USART_CR1_M0,
+        USART_CR1_M1,
+        USART_CR1_RXNEIE
+    };
+
+    res.reg = &getUARTPair(key).USARTReg->CR1;
+    return res;
+};
+
+static SHAL_UART_Baud_Rate_Generation_Register getUARTBaudRateRegister(const UART_Pair_Key key) {
+    SHAL_UART_Baud_Rate_Generation_Register res = {nullptr};
+
+    res.reg = &getUARTPair(key).USARTReg->BRR;
+    return res;
+}
+
+static SHAL_UART_ISR getUARTISR(const UART_Pair_Key key) { //TODO Support for multiple alternates for FIFO
+    SHAL_UART_ISR res = {
+        nullptr,
+        USART_ISR_TXE_TXFNF,
+        USART_ISR_TC,
+        USART_ISR_BUSY
+    };
+
+    res.reg = &getUARTPair(key).USARTReg->ISR;
+    return res;
+}
+
+static SHAL_UART_Transmit_Data_Register getUARTTransmitDataRegister(const UART_Pair_Key key) {
+    return {&getUARTPair(key).USARTReg->TDR};
+}
+
+static
+
+constexpr uint32_t getAFMask(const GPIO_Alternate_Function mask){
+    switch(mask){
+        case GPIO_Alternate_Function::AF0: return 0x00;
+        case GPIO_Alternate_Function::AF1: return 0x01;
+        case GPIO_Alternate_Function::AF2: return 0x02;
+        case GPIO_Alternate_Function::AF3: return 0x03;
+        case GPIO_Alternate_Function::AF4: return 0x04;
+        case GPIO_Alternate_Function::AF5: return 0x05;
+        case GPIO_Alternate_Function::AF6: return 0x06;
+        case GPIO_Alternate_Function::AF7: return 0x07;
+    }
+    __builtin_unreachable();
+}
+
+#endif //SHMINGO_HAL_SHAL_UART_REG_F072XB_H
--- a/SHAL/Include/Peripheral/UART/SHAL_UART.h
+++ b/SHAL/Include/Peripheral/UART/SHAL_UART.h
@@ -20,13 +20,12 @@ public:
    void init(UART_Pair_Key pair);

    //begins Tx and Usart TODO either modify this function or add a new one that supports Rx
-    void begin(uint32_t baudRate) volatile;
+    void begin(uint32_t baudRate, SHAL_USART_Word_Length wordLength) const volatile;

    //Sends a string
-    void sendString(const char* s) volatile;
+    void sendString(const char* s) const volatile;

-    //Sends a char
-    void sendChar(char c) volatile;
+    void sendChar(char c) const volatile;

 private:

--- a/SHAL/Include/Peripheral/UART/SHAL_UART_REG.h
+++ b/SHAL/Include/Peripheral/UART/SHAL_UART_REG.h
@@ -89,7 +89,52 @@
 #elif defined(STM32L4S7xx)
  #include "stm32l4s7xx.h"
 #elif defined(STM32L4S9xx)
+#elif defined(STM32H743xx)
+  #include "stm32h743xx.h"
+#elif defined(STM32H753xx)
+  #include "SHAL_UART_REG_H753ZI.h"
+#elif defined(STM32H750xx)
+  #include "stm32h750xx.h"
+#elif defined(STM32H742xx)
+  #include "stm32h742xx.h"
+#elif defined(STM32H745xx)
+  #include "stm32h745xx.h"
+#elif defined(STM32H745xG)
+  #include "stm32h745xg.h"
+#elif defined(STM32H755xx)
+  #include "stm32h755xx.h"
+#elif defined(STM32H747xx)
+  #include "stm32h747xx.h"
+#elif defined(STM32H747xG)
+  #include "stm32h747xg.h"
+#elif defined(STM32H757xx)
+  #include "stm32h757xx.h"
+#elif defined(STM32H7B0xx)
+  #include "stm32h7b0xx.h"
+#elif defined(STM32H7B0xxQ)
+  #include "stm32h7b0xxq.h"
+#elif defined(STM32H7A3xx)
+  #include "stm32h7a3xx.h"
+#elif defined(STM32H7B3xx)
+  #include "stm32h7b3xx.h"
+#elif defined(STM32H7A3xxQ)
+  #include "stm32h7a3xxq.h"
+#elif defined(STM32H7B3xxQ)
+  #include "stm32h7b3xxq.h"
+#elif defined(STM32H735xx)
+  #include "stm32h735xx.h"
+#elif defined(STM32H733xx)
+  #include "stm32h733xx.h"
+#elif defined(STM32H730xx)
+  #include "stm32h730xx.h"
+#elif defined(STM32H730xxQ)
+  #include "stm32h730xxq.h"
+#elif defined(STM32H725xx)
+  #include "stm32h725xx.h"
+#elif defined(STM32H723xx)
+  #include "stm32h723xx.h"
 #else
+
 #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
 #endif

--- a/SHAL/Include/Peripheral/UART/SHAL_UART_TYPES.h
+++ b/SHAL/Include/Peripheral/UART/SHAL_UART_TYPES.h
@@ -27,21 +27,33 @@ struct SHAL_UART_Control_Register_1 {
    uint32_t usart_enable_mask;
    uint32_t transmit_enable_mask;
    uint32_t receive_enable_mask;
+    uint32_t m0_mask;
+    uint32_t m1_mask;
+    uint32_t Rx_interrupt_enable_mask;
 };

 struct SHAL_UART_Baud_Rate_Generation_Register {
    volatile uint32_t* reg;
 };

-struct SHAL_UART_Transmit_Data_Register {
-    volatile uint16_t* reg;
-};
-
-struct SHAL_UART_ISR_FIFO_Disabled {
+struct SHAL_UART_ISR {
    volatile uint32_t* reg;
    uint32_t transmit_data_register_empty_mask;
+    uint32_t transmission_complete_mask;
+    uint32_t busy_mask;
 };

+struct SHAL_UART_Transmit_Data_Register {
+    volatile uint32_t* reg;
+};
+
+enum class SHAL_USART_Word_Length : uint32_t { //See M bits for USART
+    Bits_7 = 1 << 28,
+    Bits_8 = 0,
+    Bits_9 = 1 << 12 //Universal M bit implementation
+};
+
+


 #endif //SHMINGO_HAL_SHAL_UART_TYPES_H
--- a/SHAL/Include/SHAL.h
+++ b/SHAL/Include/SHAL.h
@@ -10,9 +10,6 @@

 #include "SHAL_TIM.h"
 #include "SHAL_GPIO.h"
-//#include "SHAL_UART.h"
-//#include "SHAL_ADC.h"
-


 #endif
--- a/SHAL/Src/STM32F0xx/Peripheral/GPIO/SHAL_GPIO.cpp
+++ b/SHAL/Src/STM32F0xx/Peripheral/GPIO/SHAL_GPIO.cpp
@@ -18,42 +18,42 @@ SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {
    SHAL_set_register_value(GPIORCCEnable.reg,GPIORCCEnable.mask);
 }

-void SHAL_GPIO::setLow() {
+void SHAL_GPIO::setLow() const {
    auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
    SHAL_set_bits(outputDataReg.reg,1,0,outputDataReg.offset);
 }

-void SHAL_GPIO::setHigh() {
+void SHAL_GPIO::setHigh() const {
    auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
    SHAL_set_bits(outputDataReg.reg,1,1,outputDataReg.offset);
 }

-void SHAL_GPIO::toggle() volatile {
+void SHAL_GPIO::toggle() const volatile {
    auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
    SHAL_flip_bits(outputDataReg.reg,1,outputDataReg.offset);
 }

-void SHAL_GPIO::setOutputType(PinType type) volatile {
+void SHAL_GPIO::setOutputType(PinType type) const volatile {
    auto outputTypeReg = getGPIOOutputTypeRegister(m_GPIO_KEY);
    SHAL_set_bits(outputTypeReg.reg,2,static_cast<uint8_t>(type),outputTypeReg.offset);
 }

-void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) volatile {
+void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) const volatile {
    auto outputSpeedReg = getGPIOOutputSpeedRegister(m_GPIO_KEY);
    SHAL_set_bits(outputSpeedReg.reg,2,static_cast<uint8_t>(speed),outputSpeedReg.offset);
 }

-void SHAL_GPIO::setInternalResistor(InternalResistorType type) volatile {
+void SHAL_GPIO::setInternalResistor(InternalResistorType type) const volatile {
    auto pupdreg = getGPIOPUPDRegister(m_GPIO_KEY);
    SHAL_set_bits(pupdreg.reg,2,static_cast<uint8_t>(type),pupdreg.offset);
 }

-void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) volatile {
+void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) const volatile {
    auto alternateFunctionReg = getGPIOAlternateFunctionRegister(m_GPIO_KEY);
    SHAL_set_bits(alternateFunctionReg.reg,4,static_cast<uint8_t>(AF),alternateFunctionReg.offset);
 }

-SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) volatile {
+SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) const volatile {
    auto pinModeReg = getGPIOModeRegister(m_GPIO_KEY);

    /*
--- a/SHAL/Src/STM32F0xx/Peripheral/Timer/SHAL_TIM.cpp
+++ b/SHAL/Src/STM32F0xx/Peripheral/Timer/SHAL_TIM.cpp
@@ -34,19 +34,19 @@ void Timer::start() {
    enableInterrupt();
 }

-void Timer::stop() {
+void Timer::stop() const {
    auto rcc_reg = getTimerRCC(m_key);

    SHAL_clear_bitmask(rcc_reg.reg,rcc_reg.enable_mask);
 }

-void Timer::setPrescaler(const uint16_t presc) const {
+void Timer::setPrescaler(const uint32_t presc) const {
    auto prescalerReg = getTimerPrescalerRegister(m_key);

    SHAL_set_bits(prescalerReg.reg,16,presc,0);
 }

-void Timer::setARR(const uint16_t arr) const {
+void Timer::setARR(const uint32_t arr) const {
    auto autoReloadReg = getTimerAutoReloadRegister(m_key);

    SHAL_set_bits(autoReloadReg.reg,16,arr,0);}
@@ -56,7 +56,7 @@ void Timer::enableInterrupt() {
    NVIC_EnableIRQ(getIRQn(m_key));
 }

-void Timer::init(uint16_t prescaler, uint16_t autoReload) {
+void Timer::init(uint32_t prescaler, uint32_t autoReload) {
    SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);

    SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
@@ -65,7 +65,7 @@ void Timer::init(uint16_t prescaler, uint16_t autoReload) {
    setARR(autoReload);
 }

-void Timer::configurePWM(SHAL_Timer_Channel channel, uint16_t prescaler, uint16_t autoReload, uint16_t captureCompareThreshold) {
+void Timer::configurePWM(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {

    setPrescaler(prescaler);
    setARR(autoReload);
@@ -76,7 +76,7 @@ void Timer::configurePWM(SHAL_Timer_Channel channel, uint16_t prescaler, uint16_
    setCaptureCompareValue(channel, captureCompareThreshold);
 }

-void Timer::configureOneshot(SHAL_Timer_Channel channel, uint16_t prescaler, uint16_t autoReload, uint16_t captureCompareThreshold) {
+void Timer::configureOneshot(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {

    setPrescaler(prescaler);
    setARR(autoReload);
@@ -87,7 +87,7 @@ void Timer::configureOneshot(SHAL_Timer_Channel channel, uint16_t prescaler, uin
    setCaptureCompareValue(channel, captureCompareThreshold);
 }

-void Timer::setOutputCompareMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode) {
+void Timer::setOutputCompareMode(SHAL_Timer_Channel channel, SHAL_TIM_Output_Compare_Mode outputCompareMode) const {

    auto channelNum = static_cast<uint8_t>(channel);

@@ -114,7 +114,7 @@ void Timer::enableChannel(SHAL_Timer_Channel channel, SHAL_Timer_Channel_Main_Ou
    SHAL_set_bits(captureCompareEnableReg.reg,16,setValue,0);
 }

-void Timer::setCaptureCompareValue(SHAL_Timer_Channel channel, uint16_t value) {
+void Timer::setCaptureCompareValue(SHAL_Timer_Channel channel, uint32_t value) const {
    auto captureCompareReg = getTimerCaptureCompareRegister(m_key,channel);

    SHAL_set_bits(captureCompareReg.reg,16,value,0);
--- a/SHAL/Src/STM32H7xx/Core/SHAL_CORE.cpp
+++ b/SHAL/Src/STM32H7xx/Core/SHAL_CORE.cpp
@@ -4,6 +4,8 @@

 #include "SHAL_CORE.h"

+#include <cassert>
+
 void SHAL_init(){
    systick_init(); //Just this for now

@@ -53,3 +55,36 @@ void SHAL_delay_ms(uint32_t ms){
        SHAL_delay_us(1000);
    }
 }
+
+bool SHAL_wait_for_bit_set_us(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
+    if(SHAL_WAIT_FOR_CONDITION_US((*reg & mask) != 0, timeout)){
+        return true;
+    }
+    return false;
+}
+
+bool SHAL_wait_for_bit_clear_us(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
+    if(SHAL_WAIT_FOR_CONDITION_US((*reg & mask) == 0, timeout)){
+        return true;
+    }
+    return false;
+}
+
+bool SHAL_wait_for_bit_set_ms(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
+    if(SHAL_WAIT_FOR_CONDITION_MS((*reg & mask) != 0, timeout)){
+        return true;
+    }
+    return false;
+}
+
+bool SHAL_wait_for_bit_clear_ms(const volatile uint32_t* reg, const uint32_t mask, const uint16_t timeout) {
+    if(SHAL_WAIT_FOR_CONDITION_MS((*reg & mask) == 0, timeout)){
+        return true;
+    }
+    return false;
+}
+
+bool SHAL_check_bit(const volatile uint32_t* reg, const uint32_t mask) {
+    if ((*reg & mask) != 0) return true;
+    return false;
+}
--- a/SHAL/Src/STM32H7xx/Peripheral/ADC/SHAL_ADC.cpp
+++ b/SHAL/Src/STM32H7xx/Peripheral/ADC/SHAL_ADC.cpp
@@ -0,0 +1,271 @@
+//
+// Created by Luca on 9/21/2025.
+//
+
+#include "SHAL_ADC.h"
+#include "SHAL_GPIO.h"
+#include "SHAL_UART.h"
+#include <cstdio>
+
+bool SHAL_ADC::isValid() const {
+    if(m_ADCKey == ADC_Key::INVALID || m_ADCKey == ADC_Key::NUM_ADC){
+        return false;
+    }
+    return true;
+}
+
+SHAL_Result SHAL_ADC::init(const ADC_Key key, SHAL_ADC_Sample_Mode mode){
+
+    m_ADCKey = key;
+
+    if(!isValid()){
+        return SHAL_Result::ERROR;
+    }
+
+    auto rcc = getADCRCCEnableRegister(m_ADCKey); //Clock enable
+    auto ccr = getADCCommonControl(m_ADCKey);
+
+    SHAL_apply_bitmask(rcc.reg,rcc.mask); //Enable clock
+
+    wakeFromDeepSleep(); //Wake and enable LDO
+
+    //Configure clock source
+    SHAL_set_bits(ccr.reg,2,static_cast<uint32_t>(SHAL_ADC_Clock_Mode::SYNC_BY_2),ccr.clock_mode_position); //TODO take as param?
+
+    configureResolution(SHAL_ADC_Resolution::B12); //Configure resolution
+    SHAL_apply_bitmask(ccr.reg,ccr.VoltageRefEnable);
+
+    if(calibrate(mode) != SHAL_Result::OKAY){ //Calibrate
+        return SHAL_Result::ERROR;
+    }
+
+    if(enable() != SHAL_Result::OKAY){
+        return SHAL_Result::ERROR;
+    }
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::calibrate(SHAL_ADC_Sample_Mode sampleMode) const {
+    const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
+
+    if(disable() != SHAL_Result::OKAY){
+        return SHAL_Result::ERROR;
+    }
+
+    SHAL_set_bits(control_reg.reg, 1, static_cast<uint32_t>(sampleMode), control_reg.sample_mode_offset); //Set sample mode (differential or single ended)
+
+    SHAL_apply_bitmask(control_reg.reg, control_reg.calibration_mask); //Start calibration
+
+    if (!SHAL_wait_for_bit_clear_us(control_reg.reg, control_reg.calibration_mask, 100)) { //Wait for calibration
+        return SHAL_Result::ERROR;
+    }
+
+    return SHAL_Result::OKAY;
+}
+
+uint32_t SHAL_ADC::singleConvertSingle(SHAL_ADC_Channel channel, SHAL_ADC_SampleTime time) const {
+
+    auto data_reg = getADCDataReg(m_ADCKey);
+    auto ISR_reg = getADCISRReg(m_ADCKey);
+
+    auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey, channel);
+
+    SHAL_set_bits(sampleTimeReg.reg, 3, static_cast<uint8_t>(time), sampleTimeReg.channel_offset); //Set sample time
+
+    if(setADCSequenceAmount(1) == SHAL_Result::ERROR) { return 0; } //Set sequence amount to 1
+
+    addADCChannelToSequence(channel, 1);
+
+    startConversion();
+
+    if (!SHAL_wait_for_bit_set_us(ISR_reg.reg, ISR_reg.end_of_conversion_mask, 200)) {
+        return 0;
+    }
+
+    uint32_t result = *data_reg.reg;
+
+    return result;
+}
+
+SHAL_Result SHAL_ADC::multiConvertSingle(SHAL_ADC_Channel* channels, int numChannels, uint16_t* result, SHAL_ADC_SampleTime time) {
+    auto data_reg = getADCDataReg(m_ADCKey); //Where our output will be stored
+
+    setADCSequenceAmount(numChannels); //Convert the correct amount of channels
+
+    for(int i = 0; i < numChannels; i++){
+        auto channel = channels[i];
+
+        auto sampleTimeReg = getADCChannelSamplingTimeRegister(m_ADCKey,channel);
+
+        SHAL_set_bits(sampleTimeReg.reg,3,static_cast<uint8_t>(time),sampleTimeReg.channel_offset); //Set sample time register TODO un-hardcode bit width?
+
+        addADCChannelToSequence(channel,i); //Use index 0 to convert channel
+    }
+
+    startConversion(); //Start ADC conversion
+
+    auto ISR_reg = getADCISRReg(m_ADCKey);
+
+    for(int i = 0; i < numChannels; i++) {
+        if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_conversion_mask) != 0),500)) { //Wait for conversion
+            return SHAL_Result::ERROR; //Failed conversion
+        }
+        result[i] = *data_reg.reg;
+    }
+
+    if (!SHAL_WAIT_FOR_CONDITION_US(((*ISR_reg.reg & ISR_reg.end_of_sequence_mask) != 0),500)) { //Wait for conversion
+        return SHAL_Result::ERROR; //Failed sequence
+    }
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::enable() const {
+
+    if(!isValid()){
+        return SHAL_Result::ERROR;
+    }
+
+    const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey);
+    const SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
+
+    SHAL_apply_bitmask(ISR_reg.reg, ISR_reg.ready_mask); //Clear ready flag (write is correct as per datasheet)
+
+    SHAL_apply_bitmask(control_reg.reg, control_reg.enable_mask); //Enable mask
+
+    if (!SHAL_wait_for_bit_set_us(ISR_reg.reg,ISR_reg.ready_mask,500)) { //Check ADRDY
+        return SHAL_Result::ERROR;
+    }
+
+    return SHAL_Result::OKAY;
+}
+
+/// Disables the ADC
+/// @return
+SHAL_Result SHAL_ADC::disable() const {
+    if(!isValid()){
+        return SHAL_Result::ERROR;
+    }
+
+    const auto control_reg = getADCControlReg(m_ADCKey);
+
+    //Stop any ongoing conversion
+    if (SHAL_check_bit(control_reg.reg, control_reg.start_mask)) {
+        SHAL_apply_bitmask(control_reg.reg, control_reg.stop_mask);
+    }
+
+    if (SHAL_check_bit(control_reg.reg,control_reg.enable_mask)) { //DO NOT disable if the ADC is already disabled
+        SHAL_apply_bitmask(control_reg.reg, control_reg.disable_mask);
+
+        if (!SHAL_wait_for_bit_clear_ms(control_reg.reg,(control_reg.enable_mask | control_reg.disable_mask),50)) {
+            return SHAL_Result::ERROR;
+        }
+    }
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::wakeFromDeepSleep() const {
+
+    const SHAL_ADC_Control_Reg control_reg = getADCControlReg(m_ADCKey); //ADC Control register
+    const SHAL_ADC_ISR_Reg ISR_reg = getADCISRReg(m_ADCKey);
+
+    SHAL_clear_bitmask(control_reg.reg,control_reg.deep_power_down_mask); //Wake ADC from sleep
+
+    SHAL_apply_bitmask(control_reg.reg,control_reg.voltage_regulator_mask);
+
+    if (!SHAL_wait_for_bit_set_us(ISR_reg.reg,ISR_reg.ldo_ready_mask,50)) { //Wait for LDO
+        return SHAL_Result::ERROR;
+    }
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::startConversion() const {
+    auto control_reg = getADCControlReg(m_ADCKey);
+
+    SHAL_apply_bitmask(control_reg.reg,control_reg.start_mask);
+
+    return SHAL_Result::OKAY;
+}
+
+
+SHAL_Result SHAL_ADC::configureResolution(SHAL_ADC_Resolution resolution) const {
+    if(!isValid()){
+        return SHAL_Result::ERROR;
+    }
+
+    const SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
+    /*
+    SHAL_set_bits(config_reg.reg,2,static_cast<uint8_t>(resolution),config_reg.resolution_offset);
+
+    char buff[20];
+    snprintf(buff,16,"CFGR: %lu\r\n", (unsigned long)ADC1->CFGR);
+    SHAL_UART3.sendString(buff);
+    */
+
+    SHAL_set_register_value(config_reg.reg, 0);
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::configureAlignment(SHAL_ADC_Alignment alignment) const {
+    if(!isValid()){
+        return SHAL_Result::ERROR;
+    }
+
+    const SHAL_ADC_Config_Reg config_reg = getADCConfigReg(m_ADCKey);
+
+    //TODO check if this needs to be abstracted (Do other platforms have >2 resolution possibilities?
+    SHAL_set_bits(config_reg.reg,1,static_cast<uint8_t>(alignment),config_reg.alignment_offset);
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::preselectChannel(SHAL_ADC_Channel channel) const {
+    auto preselect = getADCPreselectRegister(ADC_Key::S_ADC1, SHAL_ADC_Channel::CH15);
+    SHAL_set_bits(preselect.reg,1,1,preselect.channel_offset);
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::setADCSequenceAmount(uint32_t amount) const {
+    if(!isValid()){return SHAL_Result::ERROR;}
+
+    if(amount == 0){
+        return SHAL_Result::ERROR;
+    }
+
+    SHAL_ADC_Sequence_Amount_Reg sequence_amount_reg = getADCSequenceAmountRegister(m_ADCKey);
+
+    SHAL_set_bits(sequence_amount_reg.reg, 4, amount - 1, 0); //Sequence amount reg is just SQR1 least significant 4 bits, this offset should always be 0
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_Result SHAL_ADC::addADCChannelToSequence(SHAL_ADC_Channel channel, const uint32_t conversionNumber) const {
+    if(!isValid()) { return SHAL_Result::ERROR; }
+
+    auto sqr = getADCSequenceRegister(m_ADCKey, conversionNumber);
+    auto channelNum = static_cast<uint8_t>(channel);
+
+
+    SHAL_wait_for_bit_clear_ms(&ADC1->CR,ADC_CR_ADSTART,50);
+
+    SHAL_set_bits(sqr.reg, 5, channelNum, sqr.sequence_offset); //Set regular sequence register
+
+    return SHAL_Result::OKAY;
+}
+
+SHAL_ADC &ADCManager::get(ADC_Key key) {
+    return m_ADCs[static_cast<uint8_t>(key)];
+}
+
+SHAL_ADC& ADCManager::getByIndex(int index) {
+
+    if(index < static_cast<int>(ADC_Key::NUM_ADC)){
+        return m_ADCs[index];
+    }
+    return m_ADCs[0];
+}
--- a/SHAL/Src/STM32H7xx/Peripheral/GPIO/SHAL_GPIO.cpp
+++ b/SHAL/Src/STM32H7xx/Peripheral/GPIO/SHAL_GPIO.cpp
@@ -15,47 +15,49 @@ SHAL_GPIO::SHAL_GPIO(GPIO_Key key) : m_GPIO_KEY(key) {

    auto GPIORCCEnable = getGPIORCCEnable(key);

-    SHAL_set_register_value(GPIORCCEnable.reg,GPIORCCEnable.mask);
+    SHAL_apply_bitmask(GPIORCCEnable.reg,GPIORCCEnable.mask);
 }

-void SHAL_GPIO::setLow() {
+void SHAL_GPIO::setLow() const {
    auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
    SHAL_set_bits(outputDataReg.reg,1,0,outputDataReg.offset);
 }

-void SHAL_GPIO::setHigh() {
+void SHAL_GPIO::setHigh() const {
    auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
    SHAL_set_bits(outputDataReg.reg,1,1,outputDataReg.offset);
 }

-void SHAL_GPIO::toggle() volatile {
+void SHAL_GPIO::toggle() const volatile {
    auto outputDataReg = getGPIOOutputDataRegister(m_GPIO_KEY);
    SHAL_flip_bits(outputDataReg.reg,1,outputDataReg.offset);
 }

-void SHAL_GPIO::setOutputType(PinType type) volatile {
+void SHAL_GPIO::setOutputType(PinType type) const volatile {
    auto outputTypeReg = getGPIOOutputTypeRegister(m_GPIO_KEY);
    SHAL_set_bits(outputTypeReg.reg,2,static_cast<uint8_t>(type),outputTypeReg.offset);
 }

-void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) volatile {
+void SHAL_GPIO::setOutputSpeed(OutputSpeed speed) const volatile {
    auto outputSpeedReg = getGPIOOutputSpeedRegister(m_GPIO_KEY);
    SHAL_set_bits(outputSpeedReg.reg,2,static_cast<uint8_t>(speed),outputSpeedReg.offset);
 }

-void SHAL_GPIO::setInternalResistor(InternalResistorType type) volatile {
+void SHAL_GPIO::setInternalResistor(InternalResistorType type) const volatile {
    auto pupdreg = getGPIOPUPDRegister(m_GPIO_KEY);
    SHAL_set_bits(pupdreg.reg,2,static_cast<uint8_t>(type),pupdreg.offset);
 }

-void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) volatile {
+void SHAL_GPIO::setAlternateFunction(GPIO_Alternate_Function AF) const volatile {
    auto alternateFunctionReg = getGPIOAlternateFunctionRegister(m_GPIO_KEY);
    SHAL_set_bits(alternateFunctionReg.reg,4,static_cast<uint8_t>(AF),alternateFunctionReg.offset);
 }

-SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) volatile {
+SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) const volatile {
    auto pinModeReg = getGPIOModeRegister(m_GPIO_KEY);

+    GPIOManager::initGPIO(m_GPIO_KEY);
+
    /*
    if(mode == PinMode::ANALOG_MODE && getGPIOPortInfo(m_GPIO_KEY).ADCChannel == SHAL_ADC_Channel::NO_ADC_MAPPING){
        char buff[100];
@@ -69,6 +71,12 @@ SHAL_Result SHAL_GPIO::setPinMode(PinMode mode) volatile {
    return SHAL_Result::OKAY;
 }

+uint16_t SHAL_GPIO::digitalRead() const {
+    auto offset = getGPIOPinNumber(m_GPIO_KEY);
+
+    return (SHAL_check_bit(getGPIOInputDataRegister(m_GPIO_KEY).reg, 1 << offset)) ? 1 : 0;
+}
+
 /* TODO Fix implementation for STM32F072
 void SHAL_GPIO::useAsExternalInterrupt(TriggerMode mode, EXTICallback callback) {

@@ -116,10 +124,20 @@ uint16_t SHAL_GPIO::analogRead(SHAL_ADC_SampleTime sampleTime) {
    SHAL_ADC_Channel channel = getGPIOPortInfo(m_GPIO_KEY).ADCChannel;

    return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
+    return GPIOManager::getGPIOADC().singleConvertSingle(channel,sampleTime);
 }
 */

-SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
+SHAL_GPIO& GPIOManager::get(const uint8_t portNum, const uint8_t pinNum) {
+
+    uint8_t pinIndex = (PINS_PER_PORT * portNum) + pinNum;
+
+    initGPIO(static_cast<GPIO_Key>(pinIndex));
+
+    return m_gpios[portNum][pinNum];
+}
+
+void GPIOManager::initGPIO(GPIO_Key key) {

    unsigned int gpioPort = getGPIOPortNumber(key);
    uint8_t gpioPin = getGPIOPinNumber(key);
@@ -127,6 +145,12 @@ SHAL_GPIO& GPIOManager::get(GPIO_Key key) {
    if (m_gpios[gpioPort][gpioPin].m_GPIO_KEY == GPIO_Key::INVALID){
        m_gpios[gpioPort][gpioPin] = SHAL_GPIO(key);
    }
-
-    return m_gpios[gpioPort][gpioPin];
+}
+
+
+SHAL_GPIO& GPIOManager::get(const GPIO_Key key) {
+
+    initGPIO(key);
+
+    return m_gpios[getGPIOPortNumber(key)][getGPIOPinNumber(key)];
 }
--- a/SHAL/Src/STM32H7xx/Peripheral/Timer/SHAL_TIM.cpp
+++ b/SHAL/Src/STM32H7xx/Peripheral/Timer/SHAL_TIM.cpp
@@ -14,49 +14,56 @@ Timer::Timer() : m_key(Timer_Key::S_TIM_INVALID){
 }

 void Timer::start() {
-
    auto control_reg  = getTimerControlRegister1(m_key);
-    auto event_generation_reg = getTimerEventGenerationRegister(m_key);
+    auto event_reg    = getTimerEventGenerationRegister(m_key);
    auto status_reg   = getTimerStatusRegister(m_key);
-    auto break_time_dead_reg = getTimerBreakDeadTimeRegister(m_key);
-
+    auto bdtr_reg     = getTimerBreakDeadTimeRegister(m_key);
    auto rcc_reg      = getTimerRCC(m_key);

-    SHAL_apply_bitmask(control_reg.reg, control_reg.counter_enable_mask); //Enable counter
-    SHAL_apply_bitmask(control_reg.reg, control_reg.auto_reload_preload_enable_mask); //Preload enable (buffer)
-    SHAL_apply_bitmask(event_generation_reg.reg, event_generation_reg.update_generation_mask);
-
+    SHAL_apply_bitmask(event_reg.reg, event_reg.update_generation_mask);
    SHAL_clear_bitmask(status_reg.reg, status_reg.update_interrupt_flag_mask);

+    SHAL_apply_bitmask(control_reg.reg, control_reg.auto_reload_preload_enable_mask);
+
    SHAL_apply_bitmask(rcc_reg.reg, rcc_reg.enable_mask);
-    SHAL_apply_bitmask(break_time_dead_reg.reg,break_time_dead_reg.main_output_enable_mask);
+    SHAL_apply_bitmask(control_reg.reg, control_reg.counter_enable_mask);
+    SHAL_apply_bitmask(bdtr_reg.reg, bdtr_reg.main_output_enable_mask);

    enableInterrupt();
 }

 void Timer::stop() const {
-    auto rcc_reg = getTimerRCC(m_key);
+    auto control_reg = getTimerControlRegister1(m_key);

+    SHAL_clear_bitmask(control_reg.reg, control_reg.counter_enable_mask);
+    getTimerRegister(m_key)->CNT = 0;
+
+    // Force an update event to flush shadow registers NOW
+    auto event_reg = getTimerEventGenerationRegister(m_key);
+    SHAL_apply_bitmask(event_reg.reg, event_reg.update_generation_mask);
+
+    auto rcc_reg = getTimerRCC(m_key);
    SHAL_clear_bitmask(rcc_reg.reg, rcc_reg.enable_mask);
 }

-void Timer::setPrescaler(const uint16_t presc) const {
+void Timer::setPrescaler(const uint32_t presc) const {
    auto prescalerReg = getTimerPrescalerRegister(m_key);

-    SHAL_set_bits(prescalerReg.reg,16,presc,0);
+    SHAL_set_register_value(prescalerReg.reg,presc);
 }

-void Timer::setARR(const uint16_t arr) const {
+void Timer::setARR(const uint32_t arr) const {
    auto autoReloadReg = getTimerAutoReloadRegister(m_key);

-    SHAL_set_bits(autoReloadReg.reg,16,arr,0);}
+    SHAL_set_register_value(autoReloadReg.reg,arr);
+}

 void Timer::enableInterrupt() {
    getTimerRegister(m_key)->DIER |= TIM_DIER_UIE;
    NVIC_EnableIRQ(getIRQn(m_key));
 }

-void Timer::init(uint16_t prescaler, uint16_t autoReload) {
+void Timer::init(uint32_t prescaler, uint32_t autoReload) {
    SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);

    SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
@@ -65,18 +72,23 @@ void Timer::init(uint16_t prescaler, uint16_t autoReload) {
    setARR(autoReload);
 }

-void Timer::configurePWM(SHAL_Timer_Channel channel, uint16_t prescaler, uint16_t autoReload, uint16_t captureCompareThreshold) {
+void Timer::init() const {
+    SHAL_TIM_RCC_Register rcc = getTimerRCC(m_key);
+
+    SHAL_apply_bitmask(rcc.reg,rcc.enable_mask);
+}
+
+void Timer::configurePWM(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {

    setPrescaler(prescaler);
    setARR(autoReload);
+    setCaptureCompareValue(channel, captureCompareThreshold);

    setOutputCompareMode(channel, SHAL_TIM_Output_Compare_Mode::PWMMode1);
    enableChannel(channel,SHAL_Timer_Channel_Main_Output_Mode::Polarity_Normal,SHAL_Timer_Channel_Complimentary_Output_Mode::Disabled);
-
-    setCaptureCompareValue(channel, captureCompareThreshold);
 }

-void Timer::configureOneshot(SHAL_Timer_Channel channel, uint16_t prescaler, uint16_t autoReload, uint16_t captureCompareThreshold) {
+void Timer::configureOneshot(SHAL_Timer_Channel channel, uint32_t prescaler, uint32_t autoReload, uint32_t captureCompareThreshold) {

    setPrescaler(prescaler);
    setARR(autoReload);
@@ -111,13 +123,13 @@ void Timer::enableChannel(SHAL_Timer_Channel channel, SHAL_Timer_Channel_Main_Ou
    setValue |= (static_cast<uint8_t>(mainOutputMode) << ((channelNum - 1) * channelStride)); //xxBB shifted by c - 1
    setValue |= (static_cast<uint8_t>(complimentaryOutputMode) << (((channelNum - 1) * channelStride) + 2)); //BBxx shifted by c - 1

-    SHAL_set_bits(captureCompareEnableReg.reg,16,setValue,0);
+    SHAL_set_register_value(captureCompareEnableReg.reg,setValue);
 }

-void Timer::setCaptureCompareValue(SHAL_Timer_Channel channel, uint16_t value) {
+void Timer::setCaptureCompareValue(SHAL_Timer_Channel channel, uint32_t value) const {
    auto captureCompareReg = getTimerCaptureCompareRegister(m_key,channel);

-    SHAL_set_bits(captureCompareReg.reg,16,value,0);
+    SHAL_set_register_value(captureCompareReg.reg,value);
 }


--- a/SHAL/Src/STM32H7xx/Peripheral/UART/SHAL_UART.cpp
+++ b/SHAL/Src/STM32H7xx/Peripheral/UART/SHAL_UART.cpp
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    SHAL_TIM.h
+  * @author  Luca Lizaranzu
+  * @brief   Related to USART and SHAL_UART abstractions
+  ******************************************************************************
+  */
+
+
+#include "SHAL_UART.h"
+#include "SHAL_GPIO.h"
+#include "SHAL_UART_REG.h"
+
+void SHAL_UART::init(const UART_Pair_Key pair){
+
+    m_key = pair;
+
+    auto uartPair = getUARTPair(pair); //Get the UART_PAIR information to be initialized
+
+    //Get the SHAL_GPIO pins for this SHAL_UART setup
+    const GPIO_Key Tx_Key = uartPair.TxKey; //Tx pin
+    const GPIO_Key Rx_Key = uartPair.RxKey; //Rx pin
+
+    GET_GPIO(Tx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
+    GET_GPIO(Rx_Key).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
+
+    GET_GPIO(Tx_Key).setAlternateFunction(uartPair.TxAlternateFunctionMask);
+    GET_GPIO(Rx_Key).setAlternateFunction(uartPair.RxAlternateFunctionMask);
+
+
+    SHAL_UART_Enable_Register pairUARTEnable = getUARTEnableReg(pair); //Register and mask to enable the SHAL_UART channel
+
+    SHAL_apply_bitmask(pairUARTEnable.reg,pairUARTEnable.mask);
+
+
+}
+
+void SHAL_UART::begin(uint32_t baudRate, SHAL_USART_Word_Length wordLength) const volatile {
+
+    auto CR  = getUARTControlRegister1(m_key);
+    auto BRR = getUARTBaudRateRegister(m_key); // fix this
+
+    SHAL_clear_bitmask(CR.reg, CR.usart_enable_mask);
+
+    SHAL_apply_bitmask(CR.reg, static_cast<uint32_t>(wordLength));
+    SHAL_apply_bitmask(CR.reg, CR.receive_enable_mask);
+    SHAL_apply_bitmask(CR.reg, CR.transmit_enable_mask);
+    SHAL_apply_bitmask(CR.reg, CR.Rx_interrupt_enable_mask);
+
+    SHAL_set_register_value(getUARTTransmitDataRegister(m_key).reg,0); //Clear TDR
+
+    uint16_t baud = SystemCoreClock / (1 * baudRate);
+    SHAL_set_bits_16(BRR.reg, 16, baud, 0);
+
+    SHAL_apply_bitmask(CR.reg, CR.usart_enable_mask); //Enable
+}
+
+void SHAL_UART::sendString(const char *s) const volatile {
+    const auto ISR = getUARTISR(m_key);
+
+    while (*s) sendChar(*s++); //Send chars while we haven't reached end of s
+
+    if (!SHAL_wait_for_bit_set_us(ISR.reg, ISR.transmit_data_register_empty_mask, 500)) {
+        assert(false);
+    }
+}
+
+void SHAL_UART::sendChar(const char c) const volatile {
+
+    const auto ISR = getUARTISR(m_key);
+
+    SHAL_wait_for_bit_set_us(ISR.reg,ISR.transmit_data_register_empty_mask,500);
+
+    SHAL_set_register_value(getUARTTransmitDataRegister(m_key).reg,static_cast<uint32_t>(c));
+}
+
+
+
+SHAL_UART& UARTManager::get(uint8_t uart) {
+
+    if(uart > NUM_USART_LINES - 1){
+        assert(false);
+        //Memory fault
+    }
+
+    return m_UARTs[uart];
+}
--- a/SHAL/Src/User_Config.h
+++ b/SHAL/Src/User_Config.h
@@ -0,0 +1,27 @@
+//
+// Created by luca.lizaranzu on 3/20/2026.
+//
+
+#ifndef SHMINGO_HAL_USER_CONFIG_H
+#define SHMINGO_HAL_USER_CONFIG_H
+
+#include "SHAL.h"
+
+//EDIT CONFIG HERE --------------------------------------------------------------------------------------------------------------------------------------------
+
+constexpr int NUM_TIMER_GPIOS = 1;
+constexpr int NUM_ADC_PINS = 2;
+
+constexpr gpioTimerMap gpioTimerInfo[NUM_TIMER_GPIOS] = { //Add a GPIO config if you want to use it with a timer output (inverted channels not supported yet
+    {GPIO_Key::A3,"TIM2",SHAL_Timer_Channel::CH4, GPIO_Alternate_Function::AF1}
+};
+
+constexpr adcMap adcInfo[NUM_ADC_PINS] = {
+    {GPIO_Key::A1, SHAL_ADC_Channel::CH17},
+    {GPIO_Key::A3, SHAL_ADC_Channel::CH15},
+};
+
+
+//\\EDIT CONFIG HERE ------------------------------------------------------------------------------------------------------------------------------------------
+
+#endif //SHMINGO_HAL_USER_CONFIG_H
--- a/SHAL/Src/main.cpp
+++ b/SHAL/Src/main.cpp
@@ -1,24 +1,42 @@
-#include <cstdio>
 #include "SHAL.h"

 int main() {

    SHAL_init();

-    PIN(E9).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
-
-    PIN(E9).setAlternateFunction(GPIO_Alternate_Function::AF1);
-
-    SHAL_TIM1.configurePWM(SHAL_Timer_Channel::CH1,24,2000,5);
-
+    /*
+    PIN(A11).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
+    PIN(A11).setAlternateFunction(GPIO_Alternate_Function::AF2);
+    SHAL_TIM1.configurePWM(SHAL_Timer_Channel::CH4, 1000, 8000, 4000);
    SHAL_TIM1.start();
+    */

-    PIN(A3).setPinMode(PinMode::OUTPUT_MODE);
-    PIN(B0).setPinMode(PinMode::ALTERNATE_FUNCTION_MODE);
+    PIN(A11).setPinMode(PinMode::OUTPUT_MODE);
+
+    //PIN(B4).setPinMode(PinMode::OUTPUT_MODE);
+    //PIN(B4).setHigh();
+
+    RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
+
+    /* Small delay to ensure clock is stable (optional but safe) */
+    for (volatile int i = 0; i < 1000; i++);
+
+    /* 2. Set PB4 as general purpose output */
+    // MODER: 2 bits per pin → pin 4 → bits [9:8]
+    GPIOB->MODER &= ~(3U << (4 * 2));   // Clear mode bits
+    GPIOB->MODER |=  (1U << (4 * 2));   // Set as output (01)
+
+    /* 3. Set PB4 HIGH */
+    GPIOB->BSRR = (1U << 4);  // Atomic set
+
+    PIN(A11).setHigh();

    while (true) {
-        PIN(A3).toggle();
-        PIN(B0).toggle();
-        SHAL_delay_ms(500);
+
+
+        PIN(A11).toggle();
+        SHAL_delay_us(10);
+        PIN(A11).toggle();
+
    }
 }
Author	SHA1	Message	Date
Luca Lizaranzu	034361faa8	test	2026-04-02 14:09:53 -07:00
Luca Lizaranzu	36f5b37b5a	H7 working	2026-04-01 14:11:41 -07:00
Luca Lizaranzu	1b29371fff	Test program done	2026-03-20 11:41:44 -07:00
Luca Lizaranzu	303a554595	uart working but fix send char	2026-03-16 17:10:48 -07:00