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Changed UART reg structs

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This commit is contained in:
Luca Lizaranzu
2025-09-07 01:57:22 -07:00
parent 40ee0e6834
commit 465055fc53
10 changed files with 249 additions and 60 deletions
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1
CMakeLists.txt
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@@ -35,6 +35,7 @@ set(PROJECT_INCLUDE_DIRECTORIES
SHAL/Include/Peripheral/GPIO SHAL/Include/Peripheral/GPIO
SHAL/Include/Peripheral/GPIO/Reg SHAL/Include/Peripheral/GPIO/Reg
SHAL/Include/Peripheral/GPIO/UART SHAL/Include/Peripheral/GPIO/UART
SHAL/Include/Peripheral/GPIO/UART/Reg
SHAL/Include/Peripheral/EXT/ SHAL/Include/Peripheral/EXT/
${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include ${CMAKE_CURRENT_SOURCE_DIR}/SHAL/Include
) )

1
SHAL/Include/Core/SHAL_CORE.h
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@@ -52,7 +52,6 @@ struct SHAL_Peripheral_Register {
#include "stm32f071xb.h" #include "stm32f071xb.h"
#elif defined(STM32F072xB) #elif defined(STM32F072xB)
#include "stm32f072xb.h" #include "stm32f072xb.h"
#include "SHAL_TIM_REG_F072xB.h"
#elif defined(STM32F078xx) #elif defined(STM32F078xx)
#include "stm32f078xx.h" #include "stm32f078xx.h"
#elif defined(STM32F091xC) #elif defined(STM32F091xC)

1
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG.h
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@@ -28,7 +28,6 @@
#elif defined(STM32F071xB) #elif defined(STM32F071xB)
#include "stm32f071xb.h" #include "stm32f071xb.h"
#elif defined(STM32F072xB) #elif defined(STM32F072xB)
#include "stm32f072xb.h"
#include "SHAL_GPIO_REG_F072xB.h" #include "SHAL_GPIO_REG_F072xB.h"
#elif defined(STM32F078xx) #elif defined(STM32F078xx)
#include "stm32f078xx.h" #include "stm32f078xx.h"

33
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_REG_F072xB.h
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@@ -29,40 +29,7 @@ enum class GPIO_Key : uint8_t {
INVALID INVALID
}; };
//Valid usart Tx and Rx pairings for STM32F072
enum class UART_Pair : uint8_t{
//UART1
Tx1A9_Rx1A10,
Tx1B6_Rx1B7,
//UART2
Tx2A2_Rx2A3,
Tx2A14_Rx2A15,
//UART3
Tx3B10_Rx3B11,
Tx3C4_Rx3C5,
Tx3C10_Rx3C11,
//UART4
Tx4A0_Rx4A1,
Tx4C10_Rx4C11
};
constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10: return {USART1,9,10,&GPIOA->AFR[1],&GPIOA->AFR[1],AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx1B6_Rx1B7: return {USART1,6,7,&GPIOB->AFR[0],&GPIOB->AFR[0],AF_Mask::AF0,AF_Mask::AF0};
case UART_Pair::Tx2A2_Rx2A3: return {USART2,2,3,&GPIOA->AFR[0],&GPIOA->AFR[0],AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx2A14_Rx2A15: return {USART2,14,15,&GPIOA->AFR[1],&GPIOA->AFR[1],AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx3B10_Rx3B11: return {USART3,10,11,&GPIOB->AFR[1],&GPIOB->AFR[1],AF_Mask::AF4,AF_Mask::AF4};
case UART_Pair::Tx3C4_Rx3C5: return {USART3,4,5,&GPIOC->AFR[0],&GPIOC->AFR[0],AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx3C10_Rx3C11: return {USART3,10,11,&GPIOC->AFR[1],&GPIOC->AFR[1],AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx4A0_Rx4A1: return {USART4,0,1,&GPIOA->AFR[0],&GPIOA->AFR[0],AF_Mask::AF4,AF_Mask::AF4};
case UART_Pair::Tx4C10_Rx4C11: return {USART4,10,11,&GPIOC->AFR[1],&GPIOC->AFR[1],AF_Mask::AF0,AF_Mask::AF0};
}
}
constexpr SHAL_Peripheral getGPIORegister(const GPIO_Key g){ constexpr SHAL_Peripheral getGPIORegister(const GPIO_Key g){
switch(g) { switch(g) {

21
SHAL/Include/Peripheral/GPIO/Reg/SHAL_GPIO_TYPES.h
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@@ -14,27 +14,6 @@ struct SHAL_EXTIO_Register{
IRQn_Type IRQN; IRQn_Type IRQN;
}; };
enum class AF_Mask : uint8_t{
AF0 = 0x00,
AF1 = 0x01,
AF2 = 0x02,
AF3 = 0x03,
AF4 = 0x04,
AF5 = 0x05,
AF6 = 0x06,
AF7 = 0x07
};
//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping
struct SHAL_UART_Pair{
USART_TypeDef* USARTReg;
uint8_t TxPinNumber;
uint8_t RxPinNumber;
volatile uint32_t* TxReg;
volatile uint32_t* RxReg;
AF_Mask TxMask;
AF_Mask RxMask;
};
#endif //SHMINGO_HAL_SHAL_GPIO_TYPES_H #endif //SHMINGO_HAL_SHAL_GPIO_TYPES_H

57
SHAL/Include/Peripheral/GPIO/UART/Reg/SHAL_UART_REG.h Normal file
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@@ -0,0 +1,57 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_UART_REG_H
#define SHMINGO_HAL_SHAL_UART_REG_H
//
// Created by Luca on 9/6/2025.
//
#ifndef SHMINGO_HAL_SHAL_GPIO_REG_H
#define SHMINGO_HAL_SHAL_GPIO_REG_H
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "SHAL_UART_REG_F072xB.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
#endif //SHMINGO_HAL_SHAL_GPIO_REG_H
#endif //SHMINGO_HAL_SHAL_UART_REG_H

105
SHAL/Include/Peripheral/GPIO/UART/Reg/SHAL_UART_REG_F072xB.h Normal file
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@@ -0,0 +1,105 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_UART_REG_F072XB_H
#define SHMINGO_HAL_SHAL_UART_REG_F072XB_H
#include <stm32f072xb.h>
#include <cassert>
#include "SHAL_UART_TYPES.h"
#include "SHAL_GPIO_REG.h"
#define NUM_USART_LINES 4
//Valid usart Tx and Rx pairings for STM32F072
enum class UART_Pair : uint8_t{
//UART1
Tx1A9_Rx1A10,
Tx1B6_Rx1B7,
//UART2
Tx2A2_Rx2A3,
Tx2A14_Rx2A15,
//UART3
Tx3B10_Rx3B11,
Tx3C4_Rx3C5,
Tx3C10_Rx3C11,
//UART4
Tx4A0_Rx4A1,
Tx4C10_Rx4C11,
NUM_PAIRS,
INVALID
};
constexpr SHAL_UART_Pair getUARTPair(const UART_Pair pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10: return {USART1,GPIO_Key::A9,GPIO_Key::A10,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx1B6_Rx1B7: return {USART1,GPIO_Key::B6,GPIO_Key::B7,AF_Mask::AF0,AF_Mask::AF0};
case UART_Pair::Tx2A2_Rx2A3: return {USART2,GPIO_Key::A2,GPIO_Key::A3,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx2A14_Rx2A15: return {USART2,GPIO_Key::A14,GPIO_Key::A15,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx3B10_Rx3B11: return {USART3,GPIO_Key::B10,GPIO_Key::B11,AF_Mask::AF4,AF_Mask::AF4};
case UART_Pair::Tx3C4_Rx3C5: return {USART3,GPIO_Key::C4,GPIO_Key::C5,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx3C10_Rx3C11: return {USART3,GPIO_Key::C10,GPIO_Key::C11,AF_Mask::AF1,AF_Mask::AF1};
case UART_Pair::Tx4A0_Rx4A1: return {USART4,GPIO_Key::A0,GPIO_Key::A1,AF_Mask::AF4,AF_Mask::AF4};
case UART_Pair::Tx4C10_Rx4C11: return {USART4,GPIO_Key::C10,GPIO_Key::C11,AF_Mask::AF0,AF_Mask::AF0};
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
assert(false);
return {nullptr,GPIO_Key::INVALID,GPIO_Key::INVALID,AF_Mask::AF0,AF_Mask::AF0};
}
__builtin_unreachable();
}
constexpr uint8_t getUARTChannel(const UART_Pair pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10:
case UART_Pair::Tx1B6_Rx1B7:
return 0;
case UART_Pair::Tx2A2_Rx2A3:
case UART_Pair::Tx2A14_Rx2A15:
return 1;
case UART_Pair::Tx3B10_Rx3B11:
case UART_Pair::Tx3C4_Rx3C5:
case UART_Pair::Tx3C10_Rx3C11:
return 2;
case UART_Pair::Tx4A0_Rx4A1:
case UART_Pair::Tx4C10_Rx4C11:
return 3;
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
assert(false);
return 0;
}
__builtin_unreachable();
}
constexpr SHAL_UART_ENABLE_REG getUARTEnableReg(const UART_Pair pair){
switch(pair){
case UART_Pair::Tx1A9_Rx1A10:
case UART_Pair::Tx1B6_Rx1B7:
return {&RCC->APB2ENR,RCC_APB2ENR_USART1EN};
case UART_Pair::Tx2A2_Rx2A3:
case UART_Pair::Tx2A14_Rx2A15:
return {&RCC->APB1ENR,RCC_APB1ENR_USART2EN};
case UART_Pair::Tx3B10_Rx3B11:
case UART_Pair::Tx3C4_Rx3C5:
case UART_Pair::Tx3C10_Rx3C11:
return {&RCC->APB1ENR,RCC_APB1ENR_USART3EN};
case UART_Pair::Tx4A0_Rx4A1:
case UART_Pair::Tx4C10_Rx4C11:
return {&RCC->APB1ENR,RCC_APB1ENR_USART4EN};
case UART_Pair::NUM_PAIRS:
case UART_Pair::INVALID:
assert(false);
return {nullptr, 0};
}
__builtin_unreachable();
}
#endif //SHMINGO_HAL_SHAL_UART_REG_F072XB_H

37
SHAL/Include/Peripheral/GPIO/UART/Reg/SHAL_UART_TYPES.h Normal file
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@@ -0,0 +1,37 @@
//
// Created by Luca on 9/7/2025.
//
#ifndef SHMINGO_HAL_SHAL_UART_TYPES_H
#define SHMINGO_HAL_SHAL_UART_TYPES_H
#include "SHAL_CORE.h"
#include "SHAL_GPIO_REG.h"
enum class AF_Mask : uint8_t{
AF0 = 0x00,
AF1 = 0x01,
AF2 = 0x02,
AF3 = 0x03,
AF4 = 0x04,
AF5 = 0x05,
AF6 = 0x06,
AF7 = 0x07
};
//Represents a pair of pins usable for USART Tx + Rx in combination, and their alternate function mapping
struct SHAL_UART_Pair{
USART_TypeDef* USARTReg;
GPIO_Key TxKey;
GPIO_Key RxKey;
AF_Mask TxMask;
AF_Mask RxMask;
};
struct SHAL_UART_ENABLE_REG{
volatile uint32_t* USART_EN_Reg;
uint32_t USART_EN_Mask;
};
#endif //SHMINGO_HAL_SHAL_UART_TYPES_H

39
SHAL/Include/Peripheral/GPIO/UART/SHAL_UART.h
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@@ -1,19 +1,50 @@
// /**
// Created by Luca on 9/6/2025. ******************************************************************************
// * @file SHAL_TIM.h
* @author Luca Lizaranzu
* @brief Relating to UART and USART object abstractions
******************************************************************************
*/
#ifndef SHMINGO_HAL_SHAL_UART_H #ifndef SHMINGO_HAL_SHAL_UART_H
#define SHMINGO_HAL_SHAL_UART_H #define SHMINGO_HAL_SHAL_UART_H
#include "SHAL_GPIO_REG.h" #include "SHAL_UART_REG.h"
class UART{ class UART{
friend class UARTManager;
public: public:
//Sends a string
void sendString(const char* s);
//Sends a char
void sendChar(const char c);
private: private:
UART() = default; //Initializer for array
//Creates a UART based on a pair of two valid U(S)ART pins
explicit UART(const UART_Pair pair);
UART_Pair m_UARTPair = UART_Pair::INVALID;
};
class UARTManager{
public:
static UART& get(UART_Pair);
UARTManager() = delete;
private:
inline static UART m_UARTs[NUM_USART_LINES] = {};
}; };

14
SHAL/Src/Peripheral/UART/SHAL_UART.cpp Normal file
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@@ -0,0 +1,14 @@
/**
******************************************************************************
* @file SHAL_TIM.h
* @author Luca Lizaranzu
* @brief Related to USART and UART abstractions
******************************************************************************
*/
#include "SHAL_UART.h"
UART::UART(const UART_Pair pair){
}